From c80af04d7df7586352841a65a4398baf21e0c122 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Thu, 1 Mar 2012 11:37:02 -0600
Subject: x86: Fix switching of CPUs This patch prevents creation of interrupt
 controller for cpus that will be switched in later

---
 src/cpu/o3/cpu.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7f24ee988..5dd2c3f3c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -653,7 +653,7 @@ FullO3CPU<Impl>::init()
     if (icachePort.isConnected())
         fetch.setIcache();
 
-    if (FullSystem) {
+    if (FullSystem && !params()->defer_registration) {
         for (ThreadID tid = 0; tid < numThreads; tid++) {
             ThreadContext *src_tc = threadContexts[tid];
             TheISA::initCPU(src_tc, src_tc->contextId());
-- 
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