From cc614875540016b53f0bb4d5c119c7e1af159e6e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 21 Oct 2019 11:43:53 -0700 Subject: cpu: Apply the ARM TLB rework to the O3 checker CPU. The TLBs now create the stage 2 MMUs as children, and since those are specialized for instruction and data, the CPU needs to use ArmITB or ArmDTB instead of ArmTLB which is the base class without an MMU. This was changed for the BaseCPU and SimpleCPU checker already, but the TLBs are added in the O3 checker CPU as well. Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/cpu/o3/O3CPU.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 4a994f07f..89744e98a 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -181,14 +181,14 @@ class DerivO3CPU(BaseCPU): def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: - from m5.objects.ArmTLB import ArmTLB + from m5.objects.ArmTLB import ArmDTB, ArmITB self.checker = O3Checker(workload=self.workload, exitOnError=False, updateOnError=True, warnOnlyOnLoadError=True) - self.checker.itb = ArmTLB(size = self.itb.size) - self.checker.dtb = ArmTLB(size = self.dtb.size) + self.checker.itb = ArmITB(size = self.itb.size) + self.checker.dtb = ArmDTB(size = self.dtb.size) self.checker.cpu_id = self.cpu_id else: -- cgit v1.2.3