From d2c26f402cfdb9a7fd34e98e3fc7aaa48c56c99b Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 9 Jan 2012 18:08:20 -0600
Subject: O3: Add support of function tracing with O3 CPU.

---
 src/cpu/o3/commit_impl.hh | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 75ae87c75..9ff31a622 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -52,6 +52,7 @@
 #include "config/use_checker.hh"
 #include "cpu/o3/commit.hh"
 #include "cpu/o3/thread_state.hh"
+#include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/timebuf.hh"
 #include "debug/Activity.hh"
@@ -992,6 +993,8 @@ DefaultCommit<Impl>::commitInsts()
                 // Updates misc. registers.
                 head_inst->updateMiscRegs();
 
+                cpu->traceFunctions(pc[tid].instAddr());
+
                 TheISA::advancePC(pc[tid], head_inst->staticInst);
 
                 // Keep track of the last sequence number commited
-- 
cgit v1.2.3


From 525d1e46dcb3180c8d73996adc025ce255575bd7 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Mon, 9 Jan 2012 18:08:20 -0600
Subject: O3: Remove some asserts that no longer seem to be valid.

---
 src/cpu/o3/decode_impl.hh | 4 ----
 src/cpu/o3/rename_impl.hh | 4 ----
 2 files changed, 8 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 0c0ec768e..a523a8b45 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -447,10 +447,6 @@ void
 DefaultDecode<Impl>::sortInsts()
 {
     int insts_from_fetch = fromFetch->size;
-#ifdef DEBUG
-    for (ThreadID tid = 0; tid < numThreads; tid++)
-        assert(insts[tid].empty());
-#endif
     for (int i = 0; i < insts_from_fetch; ++i) {
         insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
     }
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index fc93a5197..98c0f231b 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -767,10 +767,6 @@ void
 DefaultRename<Impl>::sortInsts()
 {
     int insts_from_decode = fromDecode->size;
-#ifdef DEBUG
-    for (ThreadID tid = 0; tid < numThreads; tid++)
-        assert(insts[tid].empty());
-#endif
     for (int i = 0; i < insts_from_decode; ++i) {
         DynInstPtr inst = fromDecode->insts[i];
         insts[inst->threadNumber].push_back(inst);
-- 
cgit v1.2.3


From 9957035a42653a0666e30c744ab02fb0074db3a3 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Tue, 10 Jan 2012 10:15:02 -0600
Subject: DPRINTF: Improve some dprintf messages.

---
 src/cpu/o3/iew_impl.hh | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 9c4b1068d..92c8875e4 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1340,10 +1340,10 @@ DefaultIEW<Impl>::executeInsts()
                 fetchRedirect[tid] = true;
 
                 DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
-                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
-                        inst->predInstAddr(), inst->predNextInstAddr());
+                DPRINTF(IEW, "Predicted target was PC: %s.\n",
+                        inst->readPredTarg());
                 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
-                        inst->pcState(), inst->nextInstAddr());
+                        inst->pcState());
                 // If incorrect, then signal the ROB that it must be squashed.
                 squashDueToBranch(inst, tid);
 
-- 
cgit v1.2.3