From 14441039988265b4cb64679fcae0ddb41f1f5e32 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Thu, 1 Dec 2011 00:15:22 -0800
Subject: O3: Add stat that counts how many cycles the O3 cpu was quiesced.

--HG--
extra : rebase_source : 043b9307eef3c5b87f8e6370765641e016ed1fa7
---
 src/cpu/o3/cpu.cc | 13 +++++++++++++
 src/cpu/o3/cpu.hh |  3 +++
 2 files changed, 16 insertions(+)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 819495d62..94fc5cdf3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -442,6 +442,12 @@ FullO3CPU<Impl>::regStats()
               "to idling")
         .prereq(idleCycles);
 
+    quiesceCycles
+        .name(name() + ".quiesceCycles")
+        .desc("Total number of cycles that CPU has spent quiesced or waiting "
+              "for an interrupt")
+        .prereq(quiesceCycles);
+
     // Number of Instructions simulated
     // --------------------------------
     // Should probably be in Base CPU but need templated
@@ -688,6 +694,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
         activityRec.activity();
         fetch.wakeFromQuiesce();
 
+        quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+
         lastActivatedCycle = curTick();
 
         _status = Running;
@@ -722,6 +730,9 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
     if ((activeThreads.size() == 1 && !deallocated) ||
         activeThreads.size() == 0)
         unscheduleTickEvent();
+
+    DPRINTF(Quiesce, "Suspending Context\n");
+    lastRunningCycle = curTick();
     _status = Idle;
 }
 
@@ -1205,6 +1216,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
     }
     if (!tickEvent.scheduled())
         schedule(tickEvent, nextCycle());
+
+    lastRunningCycle = curTick();
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index dd9f5d40f..b2606c1e2 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -720,6 +720,9 @@ class FullO3CPU : public BaseO3CPU
     Stats::Scalar timesIdled;
     /** Stat for total number of cycles the CPU spends descheduled. */
     Stats::Scalar idleCycles;
+    /** Stat for total number of cycles the CPU spends descheduled due to a
+     * quiesce operation or waiting for an interrupt. */
+    Stats::Scalar quiesceCycles;
     /** Stat for the number of committed instructions per thread. */
     Stats::Vector committedInsts;
     /** Stat for the total number of committed instructions. */
-- 
cgit v1.2.3


From 61c14da751ae80e8c19e0b63ddd629c4152f1c72 Mon Sep 17 00:00:00 2001
From: Chander Sudanthi <chander.sudanthi@arm.com>
Date: Thu, 1 Dec 2011 00:15:22 -0800
Subject: O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
---
 src/cpu/o3/O3CPU.py | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 47b18a3ec..2a5b6782f 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -146,7 +146,3 @@ class DerivO3CPU(BaseCPU):
     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
     smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
-    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
-        BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
-        self.icache.tgts_per_mshr = 20
-        self.dcache.tgts_per_mshr = 20
-- 
cgit v1.2.3