From abc76f20cb98c90e8dab416dd16dfd4a954013ba Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 23 Jul 2007 21:51:38 -0700 Subject: Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed --- src/cpu/o3/alpha/cpu_builder.cc | 254 ++------------------------------------- src/cpu/o3/checker_builder.cc | 72 +----------- src/cpu/o3/cpu.cc | 18 +-- src/cpu/o3/fu_pool.cc | 25 +--- src/cpu/o3/inst_queue_impl.hh | 10 +- src/cpu/o3/mips/cpu_builder.cc | 230 ++---------------------------------- src/cpu/o3/sparc/cpu_builder.cc | 255 ++-------------------------------------- 7 files changed, 47 insertions(+), 817 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index 34754d3c5..58ee52a39 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -30,12 +30,13 @@ #include +#include "config/use_checker.hh" #include "cpu/base.hh" #include "cpu/o3/alpha/cpu.hh" #include "cpu/o3/alpha/impl.hh" #include "cpu/o3/alpha/params.hh" #include "cpu/o3/fu_pool.hh" -#include "sim/builder.hh" +#include "params/DerivO3CPU.hh" class DerivO3CPU : public AlphaO3CPU { @@ -45,245 +46,8 @@ class DerivO3CPU : public AlphaO3CPU { } }; -BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU) - - Param clock; - Param phase; - Param numThreads; -Param cpu_id; -Param activity; - -#if FULL_SYSTEM -SimObjectParam system; -SimObjectParam itb; -SimObjectParam dtb; -Param profile; - -Param do_quiesce; -Param do_checkpoint_insts; -Param do_statistics_insts; -#else -SimObjectVectorParam workload; -#endif // FULL_SYSTEM - -SimObjectParam checker; - -Param max_insts_any_thread; -Param max_insts_all_threads; -Param max_loads_any_thread; -Param max_loads_all_threads; -Param progress_interval; - -Param cachePorts; - -Param decodeToFetchDelay; -Param renameToFetchDelay; -Param iewToFetchDelay; -Param commitToFetchDelay; -Param fetchWidth; - -Param renameToDecodeDelay; -Param iewToDecodeDelay; -Param commitToDecodeDelay; -Param fetchToDecodeDelay; -Param decodeWidth; - -Param iewToRenameDelay; -Param commitToRenameDelay; -Param decodeToRenameDelay; -Param renameWidth; - -Param commitToIEWDelay; -Param renameToIEWDelay; -Param issueToExecuteDelay; -Param dispatchWidth; -Param issueWidth; -Param wbWidth; -Param wbDepth; -SimObjectParam fuPool; - -Param iewToCommitDelay; -Param renameToROBDelay; -Param commitWidth; -Param squashWidth; -Param trapLatency; - -Param backComSize; -Param forwardComSize; - -Param predType; -Param localPredictorSize; -Param localCtrBits; -Param localHistoryTableSize; -Param localHistoryBits; -Param globalPredictorSize; -Param globalCtrBits; -Param globalHistoryBits; -Param choicePredictorSize; -Param choiceCtrBits; - -Param BTBEntries; -Param BTBTagSize; - -Param RASSize; - -Param LQEntries; -Param SQEntries; -Param LFSTSize; -Param SSITSize; - -Param numPhysIntRegs; -Param numPhysFloatRegs; -Param numIQEntries; -Param numROBEntries; - -Param smtNumFetchingThreads; -Param smtFetchPolicy; -Param smtLSQPolicy; -Param smtLSQThreshold; -Param smtIQPolicy; -Param smtIQThreshold; -Param smtROBPolicy; -Param smtROBThreshold; -Param smtCommitPolicy; - -Param instShiftAmt; - -Param defer_registration; - -Param function_trace; -Param function_trace_start; - -END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU) - -BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) - - INIT_PARAM(clock, "clock speed"), - INIT_PARAM_DFLT(phase, "clock phase", 0), - INIT_PARAM(numThreads, "number of HW thread contexts"), - INIT_PARAM(cpu_id, "processor ID"), - INIT_PARAM_DFLT(activity, "Initial activity count", 0), - -#if FULL_SYSTEM - INIT_PARAM(system, "System object"), - INIT_PARAM(itb, "Instruction translation buffer"), - INIT_PARAM(dtb, "Data translation buffer"), - INIT_PARAM(profile, ""), - - INIT_PARAM(do_quiesce, ""), - INIT_PARAM(do_checkpoint_insts, ""), - INIT_PARAM(do_statistics_insts, ""), -#else - INIT_PARAM(workload, "Processes to run"), -#endif // FULL_SYSTEM - - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), - - INIT_PARAM_DFLT(max_insts_any_thread, - "Terminate when any thread reaches this inst count", - 0), - INIT_PARAM_DFLT(max_insts_all_threads, - "Terminate when all threads have reached" - "this inst count", - 0), - INIT_PARAM_DFLT(max_loads_any_thread, - "Terminate when any thread reaches this load count", - 0), - INIT_PARAM_DFLT(max_loads_all_threads, - "Terminate when all threads have reached this load" - "count", - 0), - INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), - - INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200), - - INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"), - INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"), - INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch" - "delay"), - INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"), - INIT_PARAM(fetchWidth, "Fetch width"), - INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"), - INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode" - "delay"), - INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"), - INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"), - INIT_PARAM(decodeWidth, "Decode width"), - - INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename" - "delay"), - INIT_PARAM(commitToRenameDelay, "Commit to rename delay"), - INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"), - INIT_PARAM(renameWidth, "Rename width"), - - INIT_PARAM(commitToIEWDelay, "Commit to " - "Issue/Execute/Writeback delay"), - INIT_PARAM(renameToIEWDelay, "Rename to " - "Issue/Execute/Writeback delay"), - INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal" - "to the IEW stage)"), - INIT_PARAM(dispatchWidth, "Dispatch width"), - INIT_PARAM(issueWidth, "Issue width"), - INIT_PARAM(wbWidth, "Writeback width"), - INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"), - INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL), - - INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit " - "delay"), - INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"), - INIT_PARAM(commitWidth, "Commit width"), - INIT_PARAM(squashWidth, "Squash width"), - INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6), - - INIT_PARAM(backComSize, "Time buffer size for backwards communication"), - INIT_PARAM(forwardComSize, "Time buffer size for forward communication"), - - INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"), - INIT_PARAM(localPredictorSize, "Size of local predictor"), - INIT_PARAM(localCtrBits, "Bits per counter"), - INIT_PARAM(localHistoryTableSize, "Size of local history table"), - INIT_PARAM(localHistoryBits, "Bits for the local history"), - INIT_PARAM(globalPredictorSize, "Size of global predictor"), - INIT_PARAM(globalCtrBits, "Bits per counter"), - INIT_PARAM(globalHistoryBits, "Bits of history"), - INIT_PARAM(choicePredictorSize, "Size of choice predictor"), - INIT_PARAM(choiceCtrBits, "Bits of choice counters"), - - INIT_PARAM(BTBEntries, "Number of BTB entries"), - INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"), - - INIT_PARAM(RASSize, "RAS size"), - - INIT_PARAM(LQEntries, "Number of load queue entries"), - INIT_PARAM(SQEntries, "Number of store queue entries"), - INIT_PARAM(LFSTSize, "Last fetched store table size"), - INIT_PARAM(SSITSize, "Store set ID table size"), - - INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"), - INIT_PARAM(numPhysFloatRegs, "Number of physical floating point " - "registers"), - INIT_PARAM(numIQEntries, "Number of instruction queue entries"), - INIT_PARAM(numROBEntries, "Number of reorder buffer entries"), - - INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1), - INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"), - INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"), - INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100), - INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"), - INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100), - INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"), - INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100), - INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"), - - INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"), - INIT_PARAM(defer_registration, "defer system registration (for sampling)"), - - INIT_PARAM(function_trace, "Enable function trace"), - INIT_PARAM(function_trace_start, "Cycle to start function trace") - -END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) - -CREATE_SIM_OBJECT(DerivO3CPU) +DerivO3CPU * +DerivO3CPUParams::create() { DerivO3CPU *cpu; @@ -294,8 +58,7 @@ CREATE_SIM_OBJECT(DerivO3CPU) // In non-full-system mode, we infer the number of threads from // the workload if it's not explicitly specified. int actual_num_threads = - (numThreads.isValid() && numThreads >= workload.size()) ? - numThreads : workload.size(); + (numThreads >= workload.size()) ? numThreads : workload.size(); if (workload.size() == 0) { fatal("Must specify at least one workload!"); @@ -307,7 +70,7 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->clock = clock; params->phase = phase; - params->name = getInstanceName(); + params->name = name; params->numberOfThreads = actual_num_threads; params->cpu_id = cpu_id; params->activity = activity; @@ -325,7 +88,9 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; #endif // FULL_SYSTEM +#if USE_CHECKER params->checker = checker; +#endif params->max_insts_any_thread = max_insts_any_thread; params->max_insts_all_threads = max_insts_all_threads; @@ -429,6 +194,3 @@ CREATE_SIM_OBJECT(DerivO3CPU) return cpu; } - -REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU) - diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 8b028e3a0..97425b08c 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -34,7 +34,7 @@ #include "cpu/inst_seq.hh" #include "cpu/o3/alpha/dyn_inst.hh" #include "cpu/o3/alpha/impl.hh" -#include "sim/builder.hh" +#include "params/O3Checker.hh" #include "sim/process.hh" #include "sim/sim_object.hh" @@ -58,73 +58,11 @@ class O3Checker : public Checker > // // CheckerCPU Simulation Object // -BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) - - Param max_insts_any_thread; - Param max_insts_all_threads; - Param max_loads_any_thread; - Param max_loads_all_threads; - Param progress_interval; - -#if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; - SimObjectParam system; - Param cpu_id; - Param profile; -#else - SimObjectParam workload; -#endif // FULL_SYSTEM - Param clock; - - Param defer_registration; - Param exitOnError; - Param updateOnError; - Param warnOnlyOnLoadError; - Param function_trace; - Param function_trace_start; - -END_DECLARE_SIM_OBJECT_PARAMS(O3Checker) - -BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) - - INIT_PARAM(max_insts_any_thread, - "terminate when any thread reaches this inst count"), - INIT_PARAM(max_insts_all_threads, - "terminate when all threads have reached this inst count"), - INIT_PARAM(max_loads_any_thread, - "terminate when any thread reaches this load count"), - INIT_PARAM(max_loads_all_threads, - "terminate when all threads have reached this load count"), - INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), - -#if FULL_SYSTEM - INIT_PARAM(itb, "Instruction TLB"), - INIT_PARAM(dtb, "Data TLB"), - INIT_PARAM(system, "system object"), - INIT_PARAM(cpu_id, "processor ID"), - INIT_PARAM(profile, ""), -#else - INIT_PARAM(workload, "processes to run"), -#endif // FULL_SYSTEM - - INIT_PARAM(clock, "clock speed"), - - INIT_PARAM(defer_registration, "defer system registration (for sampling)"), - INIT_PARAM(exitOnError, "exit on error"), - INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"), - INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load " - "result errors", false), - INIT_PARAM(function_trace, "Enable function trace"), - INIT_PARAM(function_trace_start, "Cycle to start function trace") - -END_INIT_SIM_OBJECT_PARAMS(O3Checker) - - -CREATE_SIM_OBJECT(O3Checker) +O3Checker * +O3CheckerParams::create() { O3Checker::Params *params = new O3Checker::Params(); - params->name = getInstanceName(); + params->name = name; params->numberOfThreads = 1; params->max_insts_any_thread = 0; params->max_insts_all_threads = 0; @@ -161,5 +99,3 @@ CREATE_SIM_OBJECT(O3Checker) O3Checker *cpu = new O3Checker(params); return cpu; } - -REGISTER_SIM_OBJECT("O3Checker", O3Checker) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 6a3eb9c43..20ed5df63 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -32,22 +32,22 @@ #include "config/full_system.hh" #include "config/use_checker.hh" -#if FULL_SYSTEM -#include "cpu/quiesce_event.hh" -#include "sim/system.hh" -#else -#include "sim/process.hh" -#endif - #include "cpu/activity.hh" #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "cpu/o3/isa_specific.hh" #include "cpu/o3/cpu.hh" - +#include "enums/MemoryMode.hh" #include "sim/core.hh" #include "sim/stat_control.hh" +#if FULL_SYSTEM +#include "cpu/quiesce_event.hh" +#include "sim/system.hh" +#else +#include "sim/process.hh" +#endif + #if USE_CHECKER #include "cpu/checker/cpu.hh" #endif @@ -882,7 +882,7 @@ FullO3CPU::resume() return; #if FULL_SYSTEM - assert(system->getMemoryMode() == System::Timing); + assert(system->getMemoryMode() == Enums::timing); #endif if (!tickEvent.scheduled()) diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc index 42e329aca..09d271b10 100644 --- a/src/cpu/o3/fu_pool.cc +++ b/src/cpu/o3/fu_pool.cc @@ -32,7 +32,7 @@ #include "cpu/o3/fu_pool.hh" #include "cpu/func_unit.hh" -#include "sim/builder.hh" +#include "params/FUPool.hh" using namespace std; @@ -275,25 +275,8 @@ FUPool::takeOverFrom() // // The FuPool object // - -BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool) - - SimObjectVectorParam FUList; - -END_DECLARE_SIM_OBJECT_PARAMS(FUPool) - - -BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool) - - INIT_PARAM(FUList, "list of FU's for this pool") - -END_INIT_SIM_OBJECT_PARAMS(FUPool) - - -CREATE_SIM_OBJECT(FUPool) +FUPool * +FUPoolParams::create() { - return new FUPool(getInstanceName(), FUList); + return new FUPool(name, FUList); } - -REGISTER_SIM_OBJECT("FUPool", FUPool) - diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index bdf5f07aa..bbdd4ddd5 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -32,10 +32,10 @@ #include #include -#include "sim/core.hh" - #include "cpu/o3/fu_pool.hh" #include "cpu/o3/inst_queue.hh" +#include "enums/OpClass.hh" +#include "sim/core.hh" template InstructionQueue::FUCompletion::FUCompletion(DynInstPtr &_inst, @@ -259,12 +259,12 @@ InstructionQueue::regStats() } */ statIssuedInstType - .init(numThreads,Num_OpClasses) + .init(numThreads,Enums::Num_OpClass) .name(name() + ".ISSUE:FU_type") .desc("Type of FU issued") .flags(total | pdf | dist) ; - statIssuedInstType.ysubnames(opClassStrings); + statIssuedInstType.ysubnames(Enums::OpClassStrings); // // How long did instructions for a particular FU type wait prior to issue @@ -297,7 +297,7 @@ InstructionQueue::regStats() .flags(pdf | dist) ; for (int i=0; i < Num_OpClasses; ++i) { - statFuBusy.subname(i, opClassStrings[i]); + statFuBusy.subname(i, Enums::OpClassStrings[i]); } fuBusy diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc index c6acc0bfb..6a30ff099 100644 --- a/src/cpu/o3/mips/cpu_builder.cc +++ b/src/cpu/o3/mips/cpu_builder.cc @@ -31,12 +31,13 @@ #include +#include "config/use_checker.hh" #include "cpu/base.hh" #include "cpu/o3/mips/cpu.hh" #include "cpu/o3/mips/impl.hh" #include "cpu/o3/mips/params.hh" #include "cpu/o3/fu_pool.hh" -#include "sim/builder.hh" +#include "params/DerivO3CPU.hh" class DerivO3CPU : public MipsO3CPU { @@ -46,229 +47,15 @@ class DerivO3CPU : public MipsO3CPU { } }; -BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU) - -Param clock; -Param phase; -Param numThreads; -Param cpu_id; -Param activity; - -SimObjectVectorParam workload; - -SimObjectParam checker; - -Param max_insts_any_thread; -Param max_insts_all_threads; -Param max_loads_any_thread; -Param max_loads_all_threads; - -Param cachePorts; - -Param decodeToFetchDelay; -Param renameToFetchDelay; -Param iewToFetchDelay; -Param commitToFetchDelay; -Param fetchWidth; - -Param renameToDecodeDelay; -Param iewToDecodeDelay; -Param commitToDecodeDelay; -Param fetchToDecodeDelay; -Param decodeWidth; - -Param iewToRenameDelay; -Param commitToRenameDelay; -Param decodeToRenameDelay; -Param renameWidth; - -Param commitToIEWDelay; -Param renameToIEWDelay; -Param issueToExecuteDelay; -Param dispatchWidth; -Param issueWidth; -Param wbWidth; -Param wbDepth; -SimObjectParam fuPool; - -Param iewToCommitDelay; -Param renameToROBDelay; -Param commitWidth; -Param squashWidth; -Param trapLatency; - -Param backComSize; -Param forwardComSize; - -Param predType; -Param localPredictorSize; -Param localCtrBits; -Param localHistoryTableSize; -Param localHistoryBits; -Param globalPredictorSize; -Param globalCtrBits; -Param globalHistoryBits; -Param choicePredictorSize; -Param choiceCtrBits; - -Param BTBEntries; -Param BTBTagSize; - -Param RASSize; - -Param LQEntries; -Param SQEntries; -Param LFSTSize; -Param SSITSize; - -Param numPhysIntRegs; -Param numPhysFloatRegs; -Param numIQEntries; -Param numROBEntries; - -Param smtNumFetchingThreads; -Param smtFetchPolicy; -Param smtLSQPolicy; -Param smtLSQThreshold; -Param smtIQPolicy; -Param smtIQThreshold; -Param smtROBPolicy; -Param smtROBThreshold; -Param smtCommitPolicy; - -Param instShiftAmt; - -Param defer_registration; - -Param function_trace; -Param function_trace_start; - -END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU) - -BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) - - INIT_PARAM(clock, "clock speed"), - INIT_PARAM_DFLT(phase, "clock phase", 0), - INIT_PARAM(numThreads, "number of HW thread contexts"), - INIT_PARAM(cpu_id, "processor ID"), - INIT_PARAM_DFLT(activity, "Initial activity count", 0), - - INIT_PARAM(workload, "Processes to run"), - - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), - - INIT_PARAM_DFLT(max_insts_any_thread, - "Terminate when any thread reaches this inst count", - 0), - INIT_PARAM_DFLT(max_insts_all_threads, - "Terminate when all threads have reached" - "this inst count", - 0), - INIT_PARAM_DFLT(max_loads_any_thread, - "Terminate when any thread reaches this load count", - 0), - INIT_PARAM_DFLT(max_loads_all_threads, - "Terminate when all threads have reached this load" - "count", - 0), - - INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200), - - INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"), - INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"), - INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch" - "delay"), - INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"), - INIT_PARAM(fetchWidth, "Fetch width"), - INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"), - INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode" - "delay"), - INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"), - INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"), - INIT_PARAM(decodeWidth, "Decode width"), - - INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename" - "delay"), - INIT_PARAM(commitToRenameDelay, "Commit to rename delay"), - INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"), - INIT_PARAM(renameWidth, "Rename width"), - - INIT_PARAM(commitToIEWDelay, "Commit to " - "Issue/Execute/Writeback delay"), - INIT_PARAM(renameToIEWDelay, "Rename to " - "Issue/Execute/Writeback delay"), - INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal" - "to the IEW stage)"), - INIT_PARAM(dispatchWidth, "Dispatch width"), - INIT_PARAM(issueWidth, "Issue width"), - INIT_PARAM(wbWidth, "Writeback width"), - INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"), - INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL), - - INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit " - "delay"), - INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"), - INIT_PARAM(commitWidth, "Commit width"), - INIT_PARAM(squashWidth, "Squash width"), - INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6), - - INIT_PARAM(backComSize, "Time buffer size for backwards communication"), - INIT_PARAM(forwardComSize, "Time buffer size for forward communication"), - - INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"), - INIT_PARAM(localPredictorSize, "Size of local predictor"), - INIT_PARAM(localCtrBits, "Bits per counter"), - INIT_PARAM(localHistoryTableSize, "Size of local history table"), - INIT_PARAM(localHistoryBits, "Bits for the local history"), - INIT_PARAM(globalPredictorSize, "Size of global predictor"), - INIT_PARAM(globalCtrBits, "Bits per counter"), - INIT_PARAM(globalHistoryBits, "Bits of history"), - INIT_PARAM(choicePredictorSize, "Size of choice predictor"), - INIT_PARAM(choiceCtrBits, "Bits of choice counters"), - - INIT_PARAM(BTBEntries, "Number of BTB entries"), - INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"), - - INIT_PARAM(RASSize, "RAS size"), - - INIT_PARAM(LQEntries, "Number of load queue entries"), - INIT_PARAM(SQEntries, "Number of store queue entries"), - INIT_PARAM(LFSTSize, "Last fetched store table size"), - INIT_PARAM(SSITSize, "Store set ID table size"), - - INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"), - INIT_PARAM(numPhysFloatRegs, "Number of physical floating point " - "registers"), - INIT_PARAM(numIQEntries, "Number of instruction queue entries"), - INIT_PARAM(numROBEntries, "Number of reorder buffer entries"), - - INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1), - INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"), - INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"), - INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100), - INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"), - INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100), - INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"), - INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100), - INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"), - - INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"), - INIT_PARAM(defer_registration, "defer system registration (for sampling)"), - - INIT_PARAM(function_trace, "Enable function trace"), - INIT_PARAM(function_trace_start, "Cycle to start function trace") - -END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) - -CREATE_SIM_OBJECT(DerivO3CPU) +DerivO3CPU * +DerivO3CPUParams::create() { DerivO3CPU *cpu; // In non-full-system mode, we infer the number of threads from // the workload if it's not explicitly specified. int actual_num_threads = - (numThreads.isValid() && numThreads >= workload.size()) ? - numThreads : workload.size(); + (numThreads >= workload.size()) ? numThreads : workload.size(); if (workload.size() == 0) { fatal("Must specify at least one workload!"); @@ -279,14 +66,16 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->clock = clock; params->phase = phase; - params->name = getInstanceName(); + params->name = name; params->numberOfThreads = actual_num_threads; params->cpu_id = cpu_id; params->activity = activity; params->workload = workload; +#if USE_CHECKER params->checker = checker; +#endif params->max_insts_any_thread = max_insts_any_thread; params->max_insts_all_threads = max_insts_all_threads; @@ -389,6 +178,3 @@ CREATE_SIM_OBJECT(DerivO3CPU) return cpu; } - -REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU) - diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc index 35badce2c..35d9e2895 100644 --- a/src/cpu/o3/sparc/cpu_builder.cc +++ b/src/cpu/o3/sparc/cpu_builder.cc @@ -30,12 +30,14 @@ #include +#include "config/full_system.hh" +#include "config/use_checker.hh" #include "cpu/base.hh" #include "cpu/o3/sparc/cpu.hh" #include "cpu/o3/sparc/impl.hh" #include "cpu/o3/sparc/params.hh" #include "cpu/o3/fu_pool.hh" -#include "sim/builder.hh" +#include "params/DerivO3CPU.hh" class DerivO3CPU : public SparcO3CPU { @@ -45,245 +47,8 @@ class DerivO3CPU : public SparcO3CPU { } }; -BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU) - - Param clock; - Param phase; - Param numThreads; - Param cpu_id; - Param activity; - -#if FULL_SYSTEM - SimObjectParam system; - SimObjectParam itb; - SimObjectParam dtb; - Param profile; - - Param do_quiesce; - Param do_checkpoint_insts; - Param do_statistics_insts; -#else - SimObjectVectorParam workload; -#endif // FULL_SYSTEM - - SimObjectParam checker; - - Param max_insts_any_thread; - Param max_insts_all_threads; - Param max_loads_any_thread; - Param max_loads_all_threads; - Param progress_interval; - - Param cachePorts; - - Param decodeToFetchDelay; - Param renameToFetchDelay; - Param iewToFetchDelay; - Param commitToFetchDelay; - Param fetchWidth; - - Param renameToDecodeDelay; - Param iewToDecodeDelay; - Param commitToDecodeDelay; - Param fetchToDecodeDelay; - Param decodeWidth; - - Param iewToRenameDelay; - Param commitToRenameDelay; - Param decodeToRenameDelay; - Param renameWidth; - - Param commitToIEWDelay; - Param renameToIEWDelay; - Param issueToExecuteDelay; - Param dispatchWidth; - Param issueWidth; - Param wbWidth; - Param wbDepth; - SimObjectParam fuPool; - - Param iewToCommitDelay; - Param renameToROBDelay; - Param commitWidth; - Param squashWidth; - Param trapLatency; - - Param backComSize; - Param forwardComSize; - - Param predType; - Param localPredictorSize; - Param localCtrBits; - Param localHistoryTableSize; - Param localHistoryBits; - Param globalPredictorSize; - Param globalCtrBits; - Param globalHistoryBits; - Param choicePredictorSize; - Param choiceCtrBits; - - Param BTBEntries; - Param BTBTagSize; - - Param RASSize; - - Param LQEntries; - Param SQEntries; - Param LFSTSize; - Param SSITSize; - - Param numPhysIntRegs; - Param numPhysFloatRegs; - Param numIQEntries; - Param numROBEntries; - - Param smtNumFetchingThreads; - Param smtFetchPolicy; - Param smtLSQPolicy; - Param smtLSQThreshold; - Param smtIQPolicy; - Param smtIQThreshold; - Param smtROBPolicy; - Param smtROBThreshold; - Param smtCommitPolicy; - - Param instShiftAmt; - - Param defer_registration; - - Param function_trace; - Param function_trace_start; - -END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU) - -BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) - - INIT_PARAM(clock, "clock speed"), - INIT_PARAM_DFLT(phase, "clock phase", 0), - INIT_PARAM(numThreads, "number of HW thread contexts"), - INIT_PARAM(cpu_id, "processor ID"), - INIT_PARAM_DFLT(activity, "Initial activity count", 0), - -#if FULL_SYSTEM - INIT_PARAM(system, "System object"), - INIT_PARAM(itb, "Instruction translation buffer"), - INIT_PARAM(dtb, "Data translation buffer"), - INIT_PARAM(profile, ""), - - INIT_PARAM(do_quiesce, ""), - INIT_PARAM(do_checkpoint_insts, ""), - INIT_PARAM(do_statistics_insts, ""), -#else - INIT_PARAM(workload, "Processes to run"), -#endif // FULL_SYSTEM - - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), - - INIT_PARAM_DFLT(max_insts_any_thread, - "Terminate when any thread reaches this inst count", - 0), - INIT_PARAM_DFLT(max_insts_all_threads, - "Terminate when all threads have reached" - "this inst count", - 0), - INIT_PARAM_DFLT(max_loads_any_thread, - "Terminate when any thread reaches this load count", - 0), - INIT_PARAM_DFLT(max_loads_all_threads, - "Terminate when all threads have reached this load" - "count", - 0), - INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), - - INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200), - - INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"), - INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"), - INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch" - "delay"), - INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"), - INIT_PARAM(fetchWidth, "Fetch width"), - INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"), - INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode" - "delay"), - INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"), - INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"), - INIT_PARAM(decodeWidth, "Decode width"), - - INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename" - "delay"), - INIT_PARAM(commitToRenameDelay, "Commit to rename delay"), - INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"), - INIT_PARAM(renameWidth, "Rename width"), - - INIT_PARAM(commitToIEWDelay, "Commit to " - "Issue/Execute/Writeback delay"), - INIT_PARAM(renameToIEWDelay, "Rename to " - "Issue/Execute/Writeback delay"), - INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal" - "to the IEW stage)"), - INIT_PARAM(dispatchWidth, "Dispatch width"), - INIT_PARAM(issueWidth, "Issue width"), - INIT_PARAM(wbWidth, "Writeback width"), - INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"), - INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL), - - INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit " - "delay"), - INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"), - INIT_PARAM(commitWidth, "Commit width"), - INIT_PARAM(squashWidth, "Squash width"), - INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6), - - INIT_PARAM(backComSize, "Time buffer size for backwards communication"), - INIT_PARAM(forwardComSize, "Time buffer size for forward communication"), - - INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"), - INIT_PARAM(localPredictorSize, "Size of local predictor"), - INIT_PARAM(localCtrBits, "Bits per counter"), - INIT_PARAM(localHistoryTableSize, "Size of local history table"), - INIT_PARAM(localHistoryBits, "Bits for the local history"), - INIT_PARAM(globalPredictorSize, "Size of global predictor"), - INIT_PARAM(globalCtrBits, "Bits per counter"), - INIT_PARAM(globalHistoryBits, "Bits of history"), - INIT_PARAM(choicePredictorSize, "Size of choice predictor"), - INIT_PARAM(choiceCtrBits, "Bits of choice counters"), - - INIT_PARAM(BTBEntries, "Number of BTB entries"), - INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"), - - INIT_PARAM(RASSize, "RAS size"), - - INIT_PARAM(LQEntries, "Number of load queue entries"), - INIT_PARAM(SQEntries, "Number of store queue entries"), - INIT_PARAM(LFSTSize, "Last fetched store table size"), - INIT_PARAM(SSITSize, "Store set ID table size"), - - INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"), - INIT_PARAM(numPhysFloatRegs, "Number of physical floating point " - "registers"), - INIT_PARAM(numIQEntries, "Number of instruction queue entries"), - INIT_PARAM(numROBEntries, "Number of reorder buffer entries"), - - INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1), - INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"), - INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"), - INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100), - INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"), - INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100), - INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"), - INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100), - INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"), - - INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"), - INIT_PARAM(defer_registration, "defer system registration (for sampling)"), - - INIT_PARAM(function_trace, "Enable function trace"), - INIT_PARAM(function_trace_start, "Cycle to start function trace") - -END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) - -CREATE_SIM_OBJECT(DerivO3CPU) +DerivO3CPU * +DerivO3CPUParams::create() { DerivO3CPU *cpu; @@ -294,8 +59,7 @@ CREATE_SIM_OBJECT(DerivO3CPU) // In non-full-system mode, we infer the number of threads from // the workload if it's not explicitly specified. int actual_num_threads = - (numThreads.isValid() && numThreads >= workload.size()) ? - numThreads : workload.size(); + (numThreads >= workload.size()) ? numThreads : workload.size(); if (workload.size() == 0) { fatal("Must specify at least one workload!"); @@ -307,7 +71,7 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->clock = clock; params->phase = phase; - params->name = getInstanceName(); + params->name = name; params->numberOfThreads = actual_num_threads; params->cpu_id = cpu_id; params->activity = activity; @@ -325,7 +89,9 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; #endif // FULL_SYSTEM +#if USE_CHECKER params->checker = checker; +#endif params->max_insts_any_thread = max_insts_any_thread; params->max_insts_all_threads = max_insts_all_threads; @@ -429,6 +195,3 @@ CREATE_SIM_OBJECT(DerivO3CPU) return cpu; } - -REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU) - -- cgit v1.2.3 From d1e533a1e243b75b3257e2f96deb385a3b10e09b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 26 Jul 2007 22:13:14 -0700 Subject: X86: Fix argument register indexing. Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f --- src/cpu/o3/alpha/cpu_impl.hh | 6 ++++-- src/cpu/o3/mips/cpu_impl.hh | 6 ++++-- src/cpu/o3/sparc/cpu_impl.hh | 6 ++++-- 3 files changed, 12 insertions(+), 6 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 1754300d2..7f8f0547b 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -293,14 +293,16 @@ template TheISA::IntReg AlphaO3CPU::getSyscallArg(int i, int tid) { - return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid); } template void AlphaO3CPU::setSyscallArg(int i, TheISA::IntReg val, int tid) { - this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid); } template diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index d1135f048..09d73b4a2 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -196,14 +196,16 @@ template TheISA::IntReg MipsO3CPU::getSyscallArg(int i, int tid) { - return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(MipsISA::ArgumentReg[i], tid); } template void MipsO3CPU::setSyscallArg(int i, IntReg val, int tid) { - this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid); } template diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 2e398577e..068057fc0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -270,8 +270,9 @@ template TheISA::IntReg SparcO3CPU::getSyscallArg(int i, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); TheISA::IntReg val = this->readArchIntReg(idx, tid); if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) val = bits(val, 31, 0); @@ -282,8 +283,9 @@ template void SparcO3CPU::setSyscallArg(int i, TheISA::IntReg val, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); this->setArchIntReg(idx, val, tid); } -- cgit v1.2.3