From f4f00c5ae98c069f79a8b56ed93284daf7532c7e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 16 Dec 2006 09:35:09 -0500 Subject: Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back. --HG-- extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919 --- src/cpu/o3/lsq_unit.hh | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index a2e11173e..0318175c3 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -561,6 +561,12 @@ LSQUnit::read(Request *req, T &data, int load_idx) // Cast this to type T? data = storeQueue[store_idx].data >> shift_amt; + // When the data comes from the store queue entry, it's in host + // order. When it gets sent to the load, it needs to be in guest + // order so when the load converts it again, it ends up back + // in host order like the inst expects. + data = TheISA::htog(data); + assert(!load_inst->memData); load_inst->memData = new uint8_t[64]; -- cgit v1.2.3