From f85286b3debf4a4a94d3b959e5bb880be81bd692 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 17 Jan 2012 12:55:08 -0600
Subject: MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
---
 src/cpu/o3/cpu.cc                 | 12 ++----------
 src/cpu/o3/cpu.hh                 |  4 ----
 src/cpu/o3/lsq.hh                 |  7 -------
 src/cpu/o3/lsq_impl.hh            | 13 -------------
 src/cpu/o3/thread_context.hh      | 10 ++++++----
 src/cpu/o3/thread_context_impl.hh |  6 +++---
 6 files changed, 11 insertions(+), 41 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 94fc5cdf3..ee0c3a88a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -610,6 +610,8 @@ FullO3CPU<Impl>::init()
     for (ThreadID tid = 0; tid < numThreads; tid++) {
         ThreadContext *src_tc = threadContexts[tid];
         TheISA::initCPU(src_tc, src_tc->contextId());
+        // Initialise the ThreadContext's memory proxies
+        thread[tid]->initMemProxies(thread[tid]->getTC());
     }
 #endif
 
@@ -974,16 +976,6 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
     this->trap(interrupt, 0, NULL);
 }
 
-template <class Impl>
-void
-FullO3CPU<Impl>::updateMemPorts()
-{
-    // Update all ThreadContext's memory ports (Functional/Virtual
-    // Ports)
-    ThreadID size = thread.size();
-    for (ThreadID i = 0; i < size; ++i)
-        thread[i]->connectMemPorts(thread[i]->getTC());
-}
 #endif
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index b2606c1e2..652e6d99a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -395,10 +395,6 @@ class FullO3CPU : public BaseO3CPU
     /** Halts the CPU. */
     void halt() { panic("Halt not implemented!\n"); }
 
-    /** Update the Virt and Phys ports of all ThreadContexts to
-     * reflect change in memory connections. */
-    void updateMemPorts();
-
     /** Check if this address is a valid instruction address. */
     bool validInstAddr(Addr addr) { return true; }
 
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 14917bc16..d01a6b0a4 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -305,8 +305,6 @@ class LSQ {
 
         bool snoopRangeSent;
 
-        virtual void setPeer(Port *port);
-
       protected:
         /** Atomic version of receive.  Panics. */
         virtual Tick recvAtomic(PacketPtr pkt);
@@ -334,11 +332,6 @@ class LSQ {
     /** D-cache port. */
     DcachePort dcachePort;
 
-#if FULL_SYSTEM
-    /** Tell the CPU to update the Phys and Virt ports. */
-    void updateMemPorts() { cpu->updateMemPorts(); }
-#endif
-
   protected:
     /** The LSQ policy for SMT mode. */
     LSQPolicy lsqPolicy;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index ef9167d8c..61dced14f 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -40,19 +40,6 @@
 
 using namespace std;
 
-template<class Impl>
-void
-LSQ<Impl>::DcachePort::setPeer(Port *port)
-{
-    Port::setPeer(port);
-
-#if FULL_SYSTEM
-    // Update the ThreadContext's memory ports (Functional/Virtual
-    // Ports)
-    lsq->updateMemPorts();
-#endif
-}
-
 template <class Impl>
 Tick
 LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 38c94439a..6ac745770 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -97,13 +97,15 @@ class O3ThreadContext : public ThreadContext
     virtual TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
 
-    virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
+    virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
 
-    virtual VirtualPort *getVirtPort();
+    virtual FSTranslatingPortProxy* getVirtProxy();
 
-    virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
+    virtual void initMemProxies(ThreadContext *tc)
+    { thread->initMemProxies(tc); }
 #else
-    virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
+    virtual SETranslatingPortProxy* getMemProxy()
+    { return thread->getMemProxy(); }
 
     /** Returns a pointer to this thread's process. */
     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 4888cf92e..4c2fee22d 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -49,10 +49,10 @@
 
 #if FULL_SYSTEM
 template <class Impl>
-VirtualPort *
-O3ThreadContext<Impl>::getVirtPort()
+FSTranslatingPortProxy*
+O3ThreadContext<Impl>::getVirtProxy()
 {
-    return thread->getVirtPort();
+    return thread->getVirtProxy();
 }
 
 template <class Impl>
-- 
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