From eb0e416998ce2546c768d2b9d9d8bf3a387a87be Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 6 Jun 2006 17:32:21 -0400 Subject: Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e --- src/cpu/ozone/cpu_impl.hh | 202 +++++++++++++++++++++++----------------------- 1 file changed, 101 insertions(+), 101 deletions(-) (limited to 'src/cpu/ozone/cpu_impl.hh') diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index c8803813d..0763a30b3 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -37,7 +37,7 @@ #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/checker/exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/exetrace.hh" #include "cpu/ozone/cpu.hh" #include "cpu/quiesce_event.hh" @@ -121,28 +121,28 @@ OzoneCPU::OzoneCPU(Params *p) #if FULL_SYSTEM checker->setSystem(p->system); #endif - checkerXC = new CheckerExecContext(&ozoneXC, checker); - thread.xcProxy = checkerXC; - xcProxy = checkerXC; + checkerTC = new CheckerThreadContext(&ozoneTC, checker); + thread.tc = checkerTC; + tc = checkerXC; } else { checker = NULL; - thread.xcProxy = &ozoneXC; - xcProxy = &ozoneXC; + thread.tc = &ozoneTC; + tc = &ozoneTC; } - ozoneXC.cpu = this; - ozoneXC.thread = &thread; + ozoneTC.cpu = this; + ozoneTC.thread = &thread; thread.inSyscall = false; - thread.setStatus(ExecContext::Suspended); + thread.setStatus(ThreadContext::Suspended); #if FULL_SYSTEM /***** All thread state stuff *****/ thread.cpu = this; thread.tid = 0; thread.mem = p->mem; - thread.quiesceEvent = new EndQuiesceEvent(xcProxy); + thread.quiesceEvent = new EndQuiesceEvent(tc); system = p->system; itb = p->itb; @@ -152,10 +152,10 @@ OzoneCPU::OzoneCPU(Params *p) if (p->profile) { thread.profile = new FunctionProfile(p->system->kernelSymtab); - // @todo: This might be better as an ExecContext instead of OzoneXC + // @todo: This might be better as an ThreadContext instead of OzoneTC Callback *cb = - new MakeCallback(&ozoneXC); + new MakeCallback(&ozoneTC); registerExitCallback(cb); } @@ -174,13 +174,13 @@ OzoneCPU::OzoneCPU(Params *p) numInst = 0; startNumInst = 0; - execContexts.push_back(xcProxy); + threadContexts.push_back(tc); frontEnd->setCPU(this); backEnd->setCPU(this); - frontEnd->setXC(xcProxy); - backEnd->setXC(xcProxy); + frontEnd->setTC(tc); + backEnd->setTC(tc); frontEnd->setThreadState(&thread); backEnd->setThreadState(&thread); @@ -263,11 +263,11 @@ OzoneCPU::takeOverFrom(BaseCPU *oldCPU) comm.advance(); } - // if any of this CPU's ExecContexts are active, mark the CPU as + // if any of this CPU's ThreadContexts are active, mark the CPU as // running and schedule its tick event. - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; - if (xc->status() == ExecContext::Active && + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; + if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; tickEvent.schedule(curTick); @@ -291,7 +291,7 @@ OzoneCPU::activateContext(int thread_num, int delay) notIdleFraction++; scheduleTickEvent(delay); _status = Running; - thread._status = ExecContext::Active; + thread._status = ThreadContext::Active; frontEnd->wakeFromQuiesce(); } @@ -381,11 +381,11 @@ OzoneCPU::init() // Mark this as in syscall so it won't need to squash thread.inSyscall = true; #if FULL_SYSTEM - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC - TheISA::initCPU(xc, xc->readCpuId()); + TheISA::initCPU(tc, tc->readCpuId()); } #endif frontEnd->renameTable.copyFrom(thread.renameTable); @@ -400,8 +400,8 @@ OzoneCPU::serialize(std::ostream &os) { BaseCPU::serialize(os); SERIALIZE_ENUM(_status); - nameOut(os, csprintf("%s.xc", name())); - ozoneXC.serialize(os); + nameOut(os, csprintf("%s.tc", name())); + ozoneTC.serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); } @@ -412,7 +412,7 @@ OzoneCPU::unserialize(Checkpoint *cp, const std::string §ion) { BaseCPU::unserialize(cp, section); UNSERIALIZE_ENUM(_status); - ozoneXC.unserialize(cp, csprintf("%s.xc", section)); + ozoneTC.unserialize(cp, csprintf("%s.tc", section)); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); } @@ -440,16 +440,16 @@ OzoneCPU::copySrcTranslate(Addr src) memReq->reset(src & ~(blk_size - 1), blk_size); // translate to physical address - Fault fault = xc->translateDataReadReq(memReq); + Fault fault = tc->translateDataReadReq(memReq); assert(fault != Alignment_Fault); if (fault == NoFault) { - xc->copySrcAddr = src; - xc->copySrcPhysAddr = memReq->paddr + offset; + tc->copySrcAddr = src; + tc->copySrcPhysAddr = memReq->paddr + offset; } else { - xc->copySrcAddr = 0; - xc->copySrcPhysAddr = 0; + tc->copySrcAddr = 0; + tc->copySrcPhysAddr = 0; } return fault; #endif @@ -467,7 +467,7 @@ OzoneCPU::copy(Addr dest) // Only support block sizes of 64 atm. assert(blk_size == 64); uint8_t data[blk_size]; - //assert(xc->copySrcAddr); + //assert(tc->copySrcAddr); int offset = dest & (blk_size - 1); // Make sure block doesn't span page @@ -480,21 +480,21 @@ OzoneCPU::copy(Addr dest) memReq->reset(dest & ~(blk_size -1), blk_size); // translate to physical address - Fault fault = xc->translateDataWriteReq(memReq); + Fault fault = tc->translateDataWriteReq(memReq); assert(fault != Alignment_Fault); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. - memReq->paddr = xc->copySrcPhysAddr; - xc->mem->read(memReq, data); + memReq->paddr = tc->copySrcPhysAddr; + tc->mem->read(memReq, data); memReq->paddr = dest_addr; - xc->mem->write(memReq, data); + tc->mem->write(memReq, data); if (dcacheInterface) { memReq->cmd = Copy; memReq->completionEvent = NULL; - memReq->paddr = xc->copySrcPhysAddr; + memReq->paddr = tc->copySrcPhysAddr; memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; @@ -510,7 +510,7 @@ template Addr OzoneCPU::dbg_vtophys(Addr addr) { - return vtophys(xcProxy, addr); + return vtophys(tcProxy, addr); } #endif // FULL_SYSTEM @@ -524,7 +524,7 @@ OzoneCPU::post_interrupt(int int_num, int index) if (_status == Idle) { DPRINTF(IPI,"Suspended Processor awoke\n"); // thread.activate(); - // Hack for now. Otherwise might have to go through the xcProxy, or + // Hack for now. Otherwise might have to go through the tc, or // I need to figure out what's the right thing to call. activateContext(thread.tid, 1); } @@ -556,10 +556,10 @@ OzoneCPU::tick() template void -OzoneCPU::squashFromXC() +OzoneCPU::squashFromTC() { thread.inSyscall = true; - backEnd->generateXCEvent(); + backEnd->generateTCEvent(); } #if !FULL_SYSTEM @@ -567,7 +567,7 @@ template void OzoneCPU::syscall() { - // Not sure this copy is needed, depending on how the XC proxy is made. + // Not sure this copy is needed, depending on how the TC proxy is made. thread.renameTable.copyFrom(backEnd->renameTable); thread.inSyscall = true; @@ -576,7 +576,7 @@ OzoneCPU::syscall() DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst); - thread.process->syscall(xcProxy); + thread.process->syscall(yc); thread.funcExeInst--; @@ -674,7 +674,7 @@ OzoneCPU::processInterrupts() checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl); } Fault fault = new InterruptFault; - fault->invoke(thread.getXCProxy()); + fault->invoke(thread.getTC()); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", thread.readMiscReg(IPR_IPLR), ipl, summary); } @@ -686,7 +686,7 @@ OzoneCPU::simPalCheck(int palFunc) { // Need to move this to ISA code // May also need to make this per thread - thread.kernelStats->callpal(palFunc, xcProxy); + thread.kernelStats->callpal(palFunc, tc); switch (palFunc) { case PAL::halt: @@ -708,14 +708,14 @@ OzoneCPU::simPalCheck(int palFunc) template BaseCPU * -OzoneCPU::OzoneXC::getCpuPtr() +OzoneCPU::OzoneTC::getCpuPtr() { return cpu; } template void -OzoneCPU::OzoneXC::setCpuId(int id) +OzoneCPU::OzoneTC::setCpuId(int id) { cpu->cpuId = id; thread->cpuId = id; @@ -723,14 +723,14 @@ OzoneCPU::OzoneXC::setCpuId(int id) template void -OzoneCPU::OzoneXC::setStatus(Status new_status) +OzoneCPU::OzoneTC::setStatus(Status new_status) { thread->_status = new_status; } template void -OzoneCPU::OzoneXC::activate(int delay) +OzoneCPU::OzoneTC::activate(int delay) { cpu->activateContext(thread->tid, delay); } @@ -738,7 +738,7 @@ OzoneCPU::OzoneXC::activate(int delay) /// Set the status to Suspended. template void -OzoneCPU::OzoneXC::suspend() +OzoneCPU::OzoneTC::suspend() { cpu->suspendContext(thread->tid); } @@ -746,7 +746,7 @@ OzoneCPU::OzoneXC::suspend() /// Set the status to Unallocated. template void -OzoneCPU::OzoneXC::deallocate() +OzoneCPU::OzoneTC::deallocate() { cpu->deallocateContext(thread->tid); } @@ -754,7 +754,7 @@ OzoneCPU::OzoneXC::deallocate() /// Set the status to Halted. template void -OzoneCPU::OzoneXC::halt() +OzoneCPU::OzoneTC::halt() { cpu->haltContext(thread->tid); } @@ -762,13 +762,13 @@ OzoneCPU::OzoneXC::halt() #if FULL_SYSTEM template void -OzoneCPU::OzoneXC::dumpFuncProfile() +OzoneCPU::OzoneTC::dumpFuncProfile() { } #endif template void -OzoneCPU::OzoneXC::takeOverFrom(ExecContext *old_context) +OzoneCPU::OzoneTC::takeOverFrom(ThreadContext *old_context) { // some things should already be set up assert(getMemPtr() == old_context->getMemPtr()); @@ -788,12 +788,12 @@ OzoneCPU::OzoneXC::takeOverFrom(ExecContext *old_context) #else EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); if (other_quiesce) { - // Point the quiesce event's XC at this XC so that it wakes up + // Point the quiesce event's TC at this TC so that it wakes up // the proper CPU. - other_quiesce->xc = this; + other_quiesce->tc = this; } if (thread->quiesceEvent) { - thread->quiesceEvent->xc = this; + thread->quiesceEvent->tc = this; } thread->kernelStats = old_context->getKernelStats(); @@ -801,12 +801,12 @@ OzoneCPU::OzoneXC::takeOverFrom(ExecContext *old_context) cpu->lockFlag = false; #endif - old_context->setStatus(ExecContext::Unallocated); + old_context->setStatus(ThreadContext::Unallocated); } template void -OzoneCPU::OzoneXC::regStats(const std::string &name) +OzoneCPU::OzoneTC::regStats(const std::string &name) { #if FULL_SYSTEM thread->kernelStats = new Kernel::Statistics(cpu->system); @@ -816,39 +816,39 @@ OzoneCPU::OzoneXC::regStats(const std::string &name) template void -OzoneCPU::OzoneXC::serialize(std::ostream &os) +OzoneCPU::OzoneTC::serialize(std::ostream &os) { } template void -OzoneCPU::OzoneXC::unserialize(Checkpoint *cp, const std::string §ion) +OzoneCPU::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion) { } #if FULL_SYSTEM template EndQuiesceEvent * -OzoneCPU::OzoneXC::getQuiesceEvent() +OzoneCPU::OzoneTC::getQuiesceEvent() { return thread->quiesceEvent; } template Tick -OzoneCPU::OzoneXC::readLastActivate() +OzoneCPU::OzoneTC::readLastActivate() { return thread->lastActivate; } template Tick -OzoneCPU::OzoneXC::readLastSuspend() +OzoneCPU::OzoneTC::readLastSuspend() { return thread->lastSuspend; } template void -OzoneCPU::OzoneXC::profileClear() +OzoneCPU::OzoneTC::profileClear() { if (thread->profile) thread->profile->clear(); @@ -856,7 +856,7 @@ OzoneCPU::OzoneXC::profileClear() template void -OzoneCPU::OzoneXC::profileSample() +OzoneCPU::OzoneTC::profileSample() { if (thread->profile) thread->profile->sample(thread->profileNode, thread->profilePC); @@ -865,7 +865,7 @@ OzoneCPU::OzoneXC::profileSample() template int -OzoneCPU::OzoneXC::getThreadNum() +OzoneCPU::OzoneTC::getThreadNum() { return thread->tid; } @@ -873,57 +873,57 @@ OzoneCPU::OzoneXC::getThreadNum() // Also somewhat obnoxious. Really only used for the TLB fault. template TheISA::MachInst -OzoneCPU::OzoneXC::getInst() +OzoneCPU::OzoneTC::getInst() { return thread->inst; } template void -OzoneCPU::OzoneXC::copyArchRegs(ExecContext *xc) +OzoneCPU::OzoneTC::copyArchRegs(ThreadContext *tc) { - thread->PC = xc->readPC(); - thread->nextPC = xc->readNextPC(); + thread->PC = tc->readPC(); + thread->nextPC = tc->readNextPC(); cpu->frontEnd->setPC(thread->PC); cpu->frontEnd->setNextPC(thread->nextPC); for (int i = 0; i < TheISA::TotalNumRegs; ++i) { if (i < TheISA::FP_Base_DepTag) { - thread->renameTable[i]->setIntResult(xc->readIntReg(i)); + thread->renameTable[i]->setIntResult(tc->readIntReg(i)); } else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) { int fp_idx = i - TheISA::FP_Base_DepTag; thread->renameTable[i]->setDoubleResult( - xc->readFloatRegDouble(fp_idx)); + tc->readFloatRegDouble(fp_idx)); } } #if !FULL_SYSTEM - thread->funcExeInst = xc->readFuncExeInst(); + thread->funcExeInst = tc->readFuncExeInst(); #endif - // Need to copy the XC values into the current rename table, + // Need to copy the TC values into the current rename table, // copy the misc regs. - thread->regs.miscRegs.copyMiscRegs(xc); + thread->regs.miscRegs.copyMiscRegs(tc); } template void -OzoneCPU::OzoneXC::clearArchRegs() +OzoneCPU::OzoneTC::clearArchRegs() { panic("Unimplemented!"); } template uint64_t -OzoneCPU::OzoneXC::readIntReg(int reg_idx) +OzoneCPU::OzoneTC::readIntReg(int reg_idx) { return thread->renameTable[reg_idx]->readIntResult(); } template float -OzoneCPU::OzoneXC::readFloatReg(int reg_idx, int width) +OzoneCPU::OzoneTC::readFloatReg(int reg_idx, int width) { int idx = reg_idx + TheISA::FP_Base_DepTag; switch(width) { @@ -939,7 +939,7 @@ OzoneCPU::OzoneXC::readFloatReg(int reg_idx, int width) template double -OzoneCPU::OzoneXC::readFloatReg(int reg_idx) +OzoneCPU::OzoneTC::readFloatReg(int reg_idx) { int idx = reg_idx + TheISA::FP_Base_DepTag; return thread->renameTable[idx]->readFloatResult(); @@ -947,7 +947,7 @@ OzoneCPU::OzoneXC::readFloatReg(int reg_idx) template uint64_t -OzoneCPU::OzoneXC::readFloatRegBits(int reg_idx, int width) +OzoneCPU::OzoneTC::readFloatRegBits(int reg_idx, int width) { int idx = reg_idx + TheISA::FP_Base_DepTag; return thread->renameTable[idx]->readIntResult(); @@ -955,7 +955,7 @@ OzoneCPU::OzoneXC::readFloatRegBits(int reg_idx, int width) template uint64_t -OzoneCPU::OzoneXC::readFloatRegBits(int reg_idx) +OzoneCPU::OzoneTC::readFloatRegBits(int reg_idx) { int idx = reg_idx + TheISA::FP_Base_DepTag; return thread->renameTable[idx]->readIntResult(); @@ -963,18 +963,18 @@ OzoneCPU::OzoneXC::readFloatRegBits(int reg_idx) template void -OzoneCPU::OzoneXC::setIntReg(int reg_idx, uint64_t val) +OzoneCPU::OzoneTC::setIntReg(int reg_idx, uint64_t val) { thread->renameTable[reg_idx]->setIntResult(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template void -OzoneCPU::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width) +OzoneCPU::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width) { int idx = reg_idx + TheISA::FP_Base_DepTag; switch(width) { @@ -989,26 +989,26 @@ OzoneCPU::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width) } if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template void -OzoneCPU::OzoneXC::setFloatReg(int reg_idx, FloatReg val) +OzoneCPU::OzoneTC::setFloatReg(int reg_idx, FloatReg val) { int idx = reg_idx + TheISA::FP_Base_DepTag; thread->renameTable[idx]->setDoubleResult(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template void -OzoneCPU::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val, +OzoneCPU::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { panic("Unimplemented!"); @@ -1016,45 +1016,45 @@ OzoneCPU::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val, template void -OzoneCPU::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val) +OzoneCPU::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val) { panic("Unimplemented!"); } template void -OzoneCPU::OzoneXC::setPC(Addr val) +OzoneCPU::OzoneTC::setPC(Addr val) { thread->PC = val; cpu->frontEnd->setPC(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template void -OzoneCPU::OzoneXC::setNextPC(Addr val) +OzoneCPU::OzoneTC::setNextPC(Addr val) { thread->nextPC = val; cpu->frontEnd->setNextPC(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template TheISA::MiscReg -OzoneCPU::OzoneXC::readMiscReg(int misc_reg) +OzoneCPU::OzoneTC::readMiscReg(int misc_reg) { return thread->regs.miscRegs.readReg(misc_reg); } template TheISA::MiscReg -OzoneCPU::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault) +OzoneCPU::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault) { return thread->regs.miscRegs.readRegWithEffect(misc_reg, fault, this); @@ -1062,13 +1062,13 @@ OzoneCPU::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault) template Fault -OzoneCPU::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val) +OzoneCPU::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode Fault ret_fault = thread->regs.miscRegs.setReg(misc_reg, val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } return ret_fault; @@ -1076,14 +1076,14 @@ OzoneCPU::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val) template Fault -OzoneCPU::OzoneXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) +OzoneCPU::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode Fault ret_fault = thread->regs.miscRegs.setRegWithEffect(misc_reg, val, this); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } return ret_fault; -- cgit v1.2.3