From 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Apr 2009 22:21:27 -0700
Subject: tlb: Don't separate the TLB classes into an instruction TLB and a
 data TLB

---
 src/cpu/ozone/front_end_impl.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/ozone/front_end_impl.hh')

diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 6b47ef539..516823b47 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
                          PC, cpu->thread->contextId());
 
     // Translate the instruction request.
-    fault = cpu->itb->translateAtomic(memReq, thread);
+    fault = cpu->itb->translateAtomic(memReq, thread, false, true);
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.
-- 
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