From 3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 10 Sep 2008 14:26:15 -0400
Subject: style: Remove non-leading tabs everywhere they shouldn't be.
 Developers should configure their editors to not insert tabs

---
 src/cpu/ozone/inorder_back_end.hh | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/cpu/ozone/inorder_back_end.hh')

diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index aef29b1e2..c23d801ba 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -222,7 +222,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
             // are executed twice.
             memReq->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
-//	    unscheduleTickEvent();
+//          unscheduleTickEvent();
             status = DcacheMissLoadStall;
             DPRINTF(IBE, "Dcache miss stall!\n");
         } else {
@@ -249,7 +249,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 
     if (fault == NoFault && dcacheInterface) {
         memReq->cmd = Write;
-//	memcpy(memReq->data,(uint8_t *)&data,memReq->size);
+//      memcpy(memReq->data,(uint8_t *)&data,memReq->size);
         memReq->completionEvent = NULL;
         memReq->time = curTick;
         memReq->flags &= ~INST_READ;
@@ -261,7 +261,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (result != MA_HIT) {
             memReq->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
-//	    unscheduleTickEvent();
+//          unscheduleTickEvent();
             status = DcacheMissStoreStall;
             DPRINTF(IBE, "Dcache miss stall!\n");
         } else {
@@ -307,7 +307,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
         if (result != MA_HIT) {
             req->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
-//	    unscheduleTickEvent();
+//          unscheduleTickEvent();
             status = DcacheMissLoadStall;
             DPRINTF(IBE, "Dcache miss load stall!\n");
         } else {
@@ -372,7 +372,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
         if (result != MA_HIT) {
             req->completionEvent = &cacheCompletionEvent;
             lastDcacheStall = curTick;
-//	    unscheduleTickEvent();
+//          unscheduleTickEvent();
             status = DcacheMissStoreStall;
             DPRINTF(IBE, "Dcache miss store stall!\n");
         } else {
-- 
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