From 47877cf2dbd6ee2f1cf9b2c609d37b0589e876ca Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 26 May 2009 09:23:13 -0700 Subject: types: add a type for thread IDs and try to use it everywhere --- src/cpu/ozone/back_end_impl.hh | 88 ++++++++++++++++++------------------- src/cpu/ozone/cpu_builder.cc | 4 +- src/cpu/ozone/inst_queue.hh | 14 +++--- src/cpu/ozone/inst_queue_impl.hh | 60 ++++++++++++------------- src/cpu/ozone/lw_back_end_impl.hh | 76 ++++++++++++++++---------------- src/cpu/ozone/null_predictor.hh | 8 ++-- src/cpu/ozone/simple_cpu_builder.cc | 4 +- 7 files changed, 127 insertions(+), 127 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh index 7753a83b5..fbb363a96 100644 --- a/src/cpu/ozone/back_end_impl.hh +++ b/src/cpu/ozone/back_end_impl.hh @@ -649,28 +649,28 @@ BackEnd::regStats() { using namespace Stats; rob_cap_events - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ROB:cap_events") .desc("number of cycles where ROB cap was active") .flags(total) ; rob_cap_inst_count - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ROB:cap_inst") .desc("number of instructions held up by ROB cap") .flags(total) ; iq_cap_events - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() +".IQ:cap_events" ) .desc("number of cycles where IQ cap was active") .flags(total) ; iq_cap_inst_count - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".IQ:cap_inst") .desc("number of instructions held up by IQ cap") .flags(total) @@ -678,49 +678,49 @@ BackEnd::regStats() exe_inst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:count") .desc("number of insts issued") .flags(total) ; exe_swp - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:swp") .desc("number of swp insts issued") .flags(total) ; exe_nop - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:nop") .desc("number of nop insts issued") .flags(total) ; exe_refs - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:refs") .desc("number of memory reference insts issued") .flags(total) ; exe_loads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:loads") .desc("number of load insts issued") .flags(total) ; exe_branches - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:branches") .desc("Number of branches issued") .flags(total) ; issued_ops - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:op_count") .desc("number of insts issued") .flags(total) @@ -737,28 +737,28 @@ BackEnd::regStats() // Other stats // lsq_forw_loads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".LSQ:forw_loads") .desc("number of loads forwarded via LSQ") .flags(total) ; inv_addr_loads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:addr_loads") .desc("number of invalid-address loads") .flags(total) ; inv_addr_swpfs - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:addr_swpfs") .desc("number of invalid-address SW prefetches") .flags(total) ; lsq_blocked_loads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".LSQ:blocked_loads") .desc("number of ready loads not issued due to memory disambiguation") .flags(total) @@ -793,28 +793,28 @@ BackEnd::regStats() } writeback_count - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:count") .desc("cumulative count of insts written-back") .flags(total) ; producer_inst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:producers") .desc("num instructions producing a value") .flags(total) ; consumer_inst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:consumers") .desc("num instructions consuming a value") .flags(total) ; wb_penalized - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:penalized") .desc("number of instrctions required to write to 'other' IQ") .flags(total) @@ -845,42 +845,42 @@ BackEnd::regStats() wb_rate = writeback_count / cpu->numCycles; stat_com_inst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:count") .desc("Number of instructions committed") .flags(total) ; stat_com_swp - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:swp_count") .desc("Number of s/w prefetches committed") .flags(total) ; stat_com_refs - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:refs") .desc("Number of memory references committed") .flags(total) ; stat_com_loads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:loads") .desc("Number of loads committed") .flags(total) ; stat_com_membars - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:membars") .desc("Number of memory barriers committed") .flags(total) ; stat_com_branches - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:branches") .desc("Number of branches committed") .flags(total) @@ -906,7 +906,7 @@ BackEnd::regStats() // we reached the BW limit // commit_eligible - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:bw_limited") .desc("number of insts not committed due to BW limits") .flags(total) @@ -923,7 +923,7 @@ BackEnd::regStats() ; ROB_count - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ROB:occupancy") .desc(name() + ".ROB occupancy (cumulative)") .flags(total) @@ -943,7 +943,7 @@ BackEnd::regStats() ROB_occ_rate = ROB_count / cpu->numCycles; ROB_occ_dist - .init(cpu->number_of_threads,0,numROBEntries,2) + .init(cpu->numThreads, 0, numROBEntries, 2) .name(name() + ".ROB:occ_dist") .desc("ROB Occupancy per cycle") .flags(total | cdf) @@ -1292,7 +1292,7 @@ BackEnd::executeInsts() // This probably needs to prioritize the redirects if a different // scheduler is used. Currently the scheduler schedules the oldest // instruction first, so the branch resolution order will be correct. - unsigned tid = inst->threadNumber; + ThreadID tid = inst->threadNumber; if (!fetchRedirect[tid]) { @@ -1735,34 +1735,34 @@ template void BackEnd::updateExeInstStats(DynInstPtr &inst) { - int thread_number = inst->threadNumber; + ThreadID tid = inst->threadNumber; // // Pick off the software prefetches // #ifdef TARGET_ALPHA if (inst->isDataPrefetch()) - exe_swp[thread_number]++; + exe_swp[tid]++; else - exe_inst[thread_number]++; + exe_inst[tid]++; #else - exe_inst[thread_number]++; + exe_inst[tid]++; #endif // // Control operations // if (inst->isControl()) - exe_branches[thread_number]++; + exe_branches[tid]++; // // Memory operations // if (inst->isMemRef()) { - exe_refs[thread_number]++; + exe_refs[tid]++; if (inst->isLoad()) - exe_loads[thread_number]++; + exe_loads[tid]++; } } @@ -1770,40 +1770,40 @@ template void BackEnd::updateComInstStats(DynInstPtr &inst) { - unsigned thread = inst->threadNumber; + ThreadID tid = inst->threadNumber; // // Pick off the software prefetches // #ifdef TARGET_ALPHA if (inst->isDataPrefetch()) { - stat_com_swp[thread]++; + stat_com_swp[tid]++; } else { - stat_com_inst[thread]++; + stat_com_inst[tid]++; } #else - stat_com_inst[thread]++; + stat_com_inst[tid]++; #endif // // Control Instructions // if (inst->isControl()) - stat_com_branches[thread]++; + stat_com_branches[tid]++; // // Memory references // if (inst->isMemRef()) { - stat_com_refs[thread]++; + stat_com_refs[tid]++; if (inst->isLoad()) { - stat_com_loads[thread]++; + stat_com_loads[tid]++; } } if (inst->isMemBarrier()) { - stat_com_membars[thread]++; + stat_com_membars[tid]++; } } diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index beb179d41..9cac3a524 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -59,11 +59,11 @@ DerivOzoneCPUParams::create() #if FULL_SYSTEM // Full-system only supports a single thread for the moment. - int actual_num_threads = 1; + ThreadID actual_num_threads = 1; #else // In non-full-system mode, we infer the number of threads from // the workload if it's not explicitly specified. - int actual_num_threads = + ThreadID actual_num_threads = numThreads.isValid() ? numThreads : workload.size(); if (workload.size() == 0) { diff --git a/src/cpu/ozone/inst_queue.hh b/src/cpu/ozone/inst_queue.hh index 5af916fb5..2f544e307 100644 --- a/src/cpu/ozone/inst_queue.hh +++ b/src/cpu/ozone/inst_queue.hh @@ -130,7 +130,7 @@ class InstQueue void setTimeBuffer(TimeBuffer *tb_ptr); /** Number of entries needed for given amount of threads. */ - int entryAmount(int num_threads); + int entryAmount(ThreadID num_threads); /** Resets max entries for all threads. */ void resetEntries(); @@ -139,13 +139,13 @@ class InstQueue unsigned numFreeEntries(); /** Returns number of free entries for a thread. */ - unsigned numFreeEntries(unsigned tid); + unsigned numFreeEntries(ThreadID tid); /** Returns whether or not the IQ is full. */ bool isFull(); /** Returns whether or not the IQ is full for a specific thread. */ - bool isFull(unsigned tid); + bool isFull(ThreadID tid); /** Returns if there are any ready instructions in the IQ. */ bool hasReadyInsts(); @@ -179,7 +179,7 @@ class InstQueue * Commits all instructions up to and including the given sequence number, * for a specific thread. */ - void commit(const InstSeqNum &inst, unsigned tid = 0); + void commit(const InstSeqNum &inst, ThreadID tid = 0); /** Wakes all dependents of a completed instruction. */ void wakeDependents(DynInstPtr &completed_inst); @@ -206,10 +206,10 @@ class InstQueue * Squashes instructions for a thread. Squashing information is obtained * from the time buffer. */ - void squash(unsigned tid); // Probably want the ISN + void squash(ThreadID tid); // Probably want the ISN /** Returns the number of used entries for a thread. */ - unsigned getCount(unsigned tid) { return count[tid]; }; + unsigned getCount(ThreadID tid) { return count[tid]; }; /** Updates the number of free entries. */ void updateFreeEntries(int num) { freeEntries += num; } @@ -219,7 +219,7 @@ class InstQueue private: /** Does the actual squashing. */ - void doSquash(unsigned tid); + void doSquash(ThreadID tid); ///////////////////////// // Various pointers diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh index 3c3084757..ae2e3b09b 100644 --- a/src/cpu/ozone/inst_queue_impl.hh +++ b/src/cpu/ozone/inst_queue_impl.hh @@ -83,8 +83,8 @@ InstQueue::InstQueue(Params *params) numThreads = 1; //Initialize thread IQ counts - for (int i = 0; i ::InstQueue(Params *params) // regScoreboard.resize(numPhysRegs); /* //Initialize Mem Dependence Units - for (int i = 0; i < numThreads; i++) { - memDepUnit[i].init(params,i); - memDepUnit[i].setIQ(this); + for (ThreadID tid = 0; tid < numThreads; tid++) { + memDepUnit[tid].init(params, tid); + memDepUnit[tid].setIQ(this); } // Initialize all the head pointers to point to NULL, and all the @@ -121,8 +121,8 @@ InstQueue::InstQueue(Params *params) regScoreboard[i] = false; } */ - for (int i = 0; i < numThreads; ++i) { - squashedSeqNum[i] = 0; + for (ThreadID tid = 0; tid < numThreads; ++tid) { + squashedSeqNum[tid] = 0; } /* for (int i = 0; i < Num_OpClasses; ++i) { @@ -141,8 +141,8 @@ InstQueue::InstQueue(Params *params) iqPolicy = Dynamic; //Set Max Entries to Total ROB Capacity - for (int i = 0; i < numThreads; i++) { - maxEntries[i] = numEntries; + for (ThreadID tid = 0; tid < numThreads; tid++) { + maxEntries[tid] = numEntries; } } else if (policy == "partitioned") { @@ -152,8 +152,8 @@ InstQueue::InstQueue(Params *params) int part_amt = numEntries / numThreads; //Divide ROB up evenly - for (int i = 0; i < numThreads; i++) { - maxEntries[i] = part_amt; + for (ThreadID tid = 0; tid < numThreads; tid++) { + maxEntries[tid] = part_amt; } DPRINTF(Fetch, "IQ sharing policy set to Partitioned:" @@ -167,8 +167,8 @@ InstQueue::InstQueue(Params *params) int thresholdIQ = (int)((double)threshold * numEntries); //Divide up by threshold amount - for (int i = 0; i < numThreads; i++) { - maxEntries[i] = thresholdIQ; + for (ThreadID tid = 0; tid < numThreads; tid++) { + maxEntries[tid] = thresholdIQ; } DPRINTF(Fetch, "IQ sharing policy set to Threshold:" @@ -292,9 +292,9 @@ InstQueue::regStats() .desc("Number of squashed non-spec instructions that were removed") .prereq(iqSquashedNonSpecRemoved); /* - for ( int i=0; i < numThreads; i++) { + for (ThreadID tid = 0; tid < numThreads; tid++) { // Tell mem dependence unit to reg stats as well. - memDepUnit[i].regStats(); + memDepUnit[tid].regStats(); } */ } @@ -327,7 +327,7 @@ InstQueue::setTimeBuffer(TimeBuffer *tb_ptr) template int -InstQueue::entryAmount(int num_threads) +InstQueue::entryAmount(ThreadID num_threads) { if (iqPolicy == Partitioned) { return numEntries / num_threads; @@ -348,7 +348,7 @@ InstQueue::resetEntries() std::list::iterator end = activeThreads->end(); while (threads != end) { - unsigned tid = *threads++; + ThreadID tid = *threads++; if (iqPolicy == Partitioned) { maxEntries[tid] = numEntries / active_threads; @@ -368,7 +368,7 @@ InstQueue::numFreeEntries() template unsigned -InstQueue::numFreeEntries(unsigned tid) +InstQueue::numFreeEntries(ThreadID tid) { return maxEntries[tid] - count[tid]; } @@ -388,7 +388,7 @@ InstQueue::isFull() template bool -InstQueue::isFull(unsigned tid) +InstQueue::isFull(ThreadID tid) { if (numFreeEntries(tid) == 0) { return(true); @@ -735,7 +735,7 @@ InstQueue::scheduleNonSpec(const InstSeqNum &inst) assert(inst_it != nonSpecInsts.end()); -// unsigned tid = (*inst_it).second->threadNumber; +// ThreadID tid = (*inst_it).second->threadNumber; // Mark this instruction as ready to issue. (*inst_it).second->setCanIssue(); @@ -752,7 +752,7 @@ InstQueue::scheduleNonSpec(const InstSeqNum &inst) template void -InstQueue::commit(const InstSeqNum &inst, unsigned tid) +InstQueue::commit(const InstSeqNum &inst, ThreadID tid) { /*Need to go through each thread??*/ DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", @@ -879,7 +879,7 @@ template void InstQueue::completeMemInst(DynInstPtr &completed_inst) { - int tid = completed_inst->threadNumber; + ThreadID tid = completed_inst->threadNumber; DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", completed_inst->readPC(), completed_inst->seqNum); @@ -903,7 +903,7 @@ InstQueue::violation(DynInstPtr &store, */ template void -InstQueue::squash(unsigned tid) +InstQueue::squash(ThreadID tid) { DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " "the IQ.\n", tid); @@ -927,7 +927,7 @@ InstQueue::squash(unsigned tid) template void -InstQueue::doSquash(unsigned tid) +InstQueue::doSquash(ThreadID tid) { // Make sure the squashed sequence number is valid. assert(squashedSeqNum[tid] != 0); @@ -1200,10 +1200,10 @@ InstQueue::countInsts() #if 0 int total_insts = 0; - for (int i = 0; i < numThreads; ++i) { - ListIt count_it = instList[i].begin(); + for (ThreadID tid = 0; tid < numThreads; ++tid) { + ListIt count_it = instList[tid].begin(); - while (count_it != instList[i].end()) { + while (count_it != instList[tid].end()) { if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { if (!(*count_it)->isIssued()) { ++total_insts; @@ -1300,13 +1300,13 @@ template void InstQueue::dumpInsts() { - for (int i = 0; i < numThreads; ++i) { + for (ThreadID tid = 0; tid < numThreads; ++tid) { // int num = 0; // int valid_num = 0; /* - ListIt inst_list_it = instList[i].begin(); + ListIt inst_list_it = instList[tid].begin(); - while (inst_list_it != instList[i].end()) + while (inst_list_it != instList[tid].end()) { cprintf("Instruction:%i\n", num); diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index 60c42edd3..86d4531a0 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -188,77 +188,77 @@ LWBackEnd::regStats() LSQ.regStats(); robCapEvents - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ROB:cap_events") .desc("number of cycles where ROB cap was active") .flags(total) ; robCapInstCount - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ROB:cap_inst") .desc("number of instructions held up by ROB cap") .flags(total) ; iqCapEvents - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() +".IQ:cap_events" ) .desc("number of cycles where IQ cap was active") .flags(total) ; iqCapInstCount - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".IQ:cap_inst") .desc("number of instructions held up by IQ cap") .flags(total) ; exeInst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:count") .desc("number of insts issued") .flags(total) ; exeSwp - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:swp") .desc("number of swp insts issued") .flags(total) ; exeNop - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:nop") .desc("number of nop insts issued") .flags(total) ; exeRefs - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:refs") .desc("number of memory reference insts issued") .flags(total) ; exeLoads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:loads") .desc("number of load insts issued") .flags(total) ; exeBranches - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:branches") .desc("Number of branches issued") .flags(total) ; issuedOps - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:op_count") .desc("number of insts issued") .flags(total) @@ -275,28 +275,28 @@ LWBackEnd::regStats() // Other stats // lsqForwLoads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".LSQ:forw_loads") .desc("number of loads forwarded via LSQ") .flags(total) ; invAddrLoads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:addr_loads") .desc("number of invalid-address loads") .flags(total) ; invAddrSwpfs - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ISSUE:addr_swpfs") .desc("number of invalid-address SW prefetches") .flags(total) ; lsqBlockedLoads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".LSQ:blocked_loads") .desc("number of ready loads not issued due to memory disambiguation") .flags(total) @@ -332,28 +332,28 @@ LWBackEnd::regStats() } */ writebackCount - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:count") .desc("cumulative count of insts written-back") .flags(total) ; producerInst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:producers") .desc("num instructions producing a value") .flags(total) ; consumerInst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:consumers") .desc("num instructions consuming a value") .flags(total) ; wbPenalized - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".WB:penalized") .desc("number of instrctions required to write to 'other' IQ") .flags(total) @@ -384,42 +384,42 @@ LWBackEnd::regStats() wbRate = writebackCount / cpu->numCycles; statComInst - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:count") .desc("Number of instructions committed") .flags(total) ; statComSwp - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:swp_count") .desc("Number of s/w prefetches committed") .flags(total) ; statComRefs - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:refs") .desc("Number of memory references committed") .flags(total) ; statComLoads - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:loads") .desc("Number of loads committed") .flags(total) ; statComMembars - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:membars") .desc("Number of memory barriers committed") .flags(total) ; statComBranches - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:branches") .desc("Number of branches committed") .flags(total) @@ -445,7 +445,7 @@ LWBackEnd::regStats() // we reached the BW limit // commitEligible - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:bw_limited") .desc("number of insts not committed due to BW limits") .flags(total) @@ -457,13 +457,13 @@ LWBackEnd::regStats() ; squashedInsts - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:squashed_insts") .desc("Number of instructions removed from inst list") ; ROBSquashedInsts - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".COM:rob_squashed_insts") .desc("Number of instructions removed from inst list when they reached the head of the ROB") ; @@ -474,7 +474,7 @@ LWBackEnd::regStats() ; ROBCount - .init(cpu->number_of_threads) + .init(cpu->numThreads) .name(name() + ".ROB:occupancy") .desc(name() + ".ROB occupancy (cumulative)") .flags(total) @@ -494,7 +494,7 @@ LWBackEnd::regStats() ROBOccRate = ROBCount / cpu->numCycles; /* ROBOccDist - .init(cpu->number_of_threads,0,numROBEntries,2) + .init(cpu->numThreads, 0, numROBEntries, 2) .name(name() + ".ROB:occ_dist") .desc("ROB Occupancy per cycle") .flags(total | cdf) @@ -1498,34 +1498,34 @@ template void LWBackEnd::updateExeInstStats(DynInstPtr &inst) { - int thread_number = inst->threadNumber; + ThreadID tid = inst->threadNumber; // // Pick off the software prefetches // #ifdef TARGET_ALPHA if (inst->isDataPrefetch()) - exeSwp[thread_number]++; + exeSwp[tid]++; else - exeInst[thread_number]++; + exeInst[tid]++; #else - exeInst[thread_number]++; + exeInst[tid]++; #endif // // Control operations // if (inst->isControl()) - exeBranches[thread_number]++; + exeBranches[tid]++; // // Memory operations // if (inst->isMemRef()) { - exeRefs[thread_number]++; + exeRefs[tid]++; if (inst->isLoad()) - exeLoads[thread_number]++; + exeLoads[tid]++; } } @@ -1533,7 +1533,7 @@ template void LWBackEnd::updateComInstStats(DynInstPtr &inst) { - unsigned tid = inst->threadNumber; + ThreadID tid = inst->threadNumber; // keep an instruction count thread->numInst++; diff --git a/src/cpu/ozone/null_predictor.hh b/src/cpu/ozone/null_predictor.hh index 68bb7cd52..44d2f5475 100644 --- a/src/cpu/ozone/null_predictor.hh +++ b/src/cpu/ozone/null_predictor.hh @@ -68,7 +68,7 @@ class NullPredictor * @param tid The thread id. * @return Returns if the branch is taken or not. */ - bool predict(DynInstPtr &inst, Addr &PC, unsigned tid) + bool predict(DynInstPtr &inst, Addr &PC, ThreadID tid) { return false; } /** @@ -77,7 +77,7 @@ class NullPredictor * @param done_sn The sequence number to commit any older updates up until. * @param tid The thread id. */ - void update(const InstSeqNum &done_sn, unsigned tid) { } + void update(const InstSeqNum &done_sn, ThreadID tid) { } /** * Squashes all outstanding updates until a given sequence number. @@ -85,7 +85,7 @@ class NullPredictor * until. * @param tid The thread id. */ - void squash(const InstSeqNum &squashed_sn, unsigned tid) { } + void squash(const InstSeqNum &squashed_sn, ThreadID tid) { } /** * Squashes all outstanding updates until a given sequence number, and @@ -97,7 +97,7 @@ class NullPredictor * @param tid The thread id. */ void squash(const InstSeqNum &squashed_sn, const Addr &corr_target, - bool actually_taken, unsigned tid) + bool actually_taken, ThreadID tid) { } }; diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc index fa83e2531..2fc7c10d0 100644 --- a/src/cpu/ozone/simple_cpu_builder.cc +++ b/src/cpu/ozone/simple_cpu_builder.cc @@ -62,11 +62,11 @@ SimpleOzoneCPUParams::create() #if FULL_SYSTEM // Full-system only supports a single thread for the moment. - int actual_num_threads = 1; + ThreadID actual_num_threads = 1; #else // In non-full-system mode, we infer the number of threads from // the workload if it's not explicitly specified. - int actual_num_threads = + ThreadID actual_num_threads = numThreads.isValid() ? numThreads : workload.size(); if (workload.size() == 0) { -- cgit v1.2.3