From 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Apr 2009 22:21:27 -0700
Subject: tlb: Don't separate the TLB classes into an instruction TLB and a
 data TLB

---
 src/cpu/ozone/cpu.hh            | 11 +++++------
 src/cpu/ozone/front_end_impl.hh |  2 +-
 src/cpu/ozone/simple_params.hh  |  5 ++---
 3 files changed, 8 insertions(+), 10 deletions(-)

(limited to 'src/cpu/ozone')

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 0bfb4bfa9..af62f863a 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -53,8 +53,7 @@
 
 namespace TheISA
 {
-    class ITB;
-    class DTB;
+    class TLB;
 }
 class PhysicalMemory;
 class MemoryController;
@@ -116,9 +115,9 @@ class OzoneCPU : public BaseCPU
 
         BaseCPU *getCpuPtr();
 
-        TheISA::ITB *getITBPtr() { return cpu->itb; }
+        TheISA::TLB *getITBPtr() { return cpu->itb; }
 
-        TheISA::DTB * getDTBPtr() { return cpu->dtb; }
+        TheISA::TLB * getDTBPtr() { return cpu->dtb; }
 
 #if FULL_SYSTEM
         System *getSystemPtr() { return cpu->system; }
@@ -349,8 +348,8 @@ class OzoneCPU : public BaseCPU
 
     bool interval_stats;
 
-    TheISA::ITB *itb;
-    TheISA::DTB *dtb;
+    TheISA::TLB *itb;
+    TheISA::TLB *dtb;
     System *system;
     PhysicalMemory *physmem;
 #endif
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 6b47ef539..516823b47 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
                          PC, cpu->thread->contextId());
 
     // Translate the instruction request.
-    fault = cpu->itb->translateAtomic(memReq, thread);
+    fault = cpu->itb->translateAtomic(memReq, thread, false, true);
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index ec5782c8a..7687fdf60 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -36,8 +36,7 @@
 //Forward declarations
 namespace TheISA
 {
-    class DTB;
-    class ITB;
+    class TLB;
 }
 class FUPool;
 class MemObject;
@@ -55,7 +54,7 @@ class SimpleParams : public BaseCPU::Params
 {
   public:
 
-    TheISA::ITB *itb; TheISA::DTB *dtb;
+    TheISA::TLB *itb; TheISA::TLB *dtb;
 #if !FULL_SYSTEM
     std::vector<Process *> workload;
 #endif // FULL_SYSTEM
-- 
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