From 038217049a952a67f29b79c416a35d89fea31f70 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 03:37:01 -0500 Subject: Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions. --HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9 --- src/cpu/ozone/cpu.hh | 2 -- src/cpu/ozone/dyn_inst.hh | 2 -- src/cpu/ozone/dyn_inst_impl.hh | 14 -------------- 3 files changed, 18 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 70ec1d101..bd46b198b 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -583,8 +583,6 @@ class OzoneCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei(); - int readIntrFlag() { return thread.intrflag; } - void setIntrFlag(int val) { thread.intrflag = val; } bool inPalMode() { return AlphaISA::PcPAL(thread.PC); } bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); } bool simPalCheck(int palFunc); diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index e7390626e..d3871568a 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -238,8 +238,6 @@ class OzoneDynInst : public BaseDynInst #if FULL_SYSTEM Fault hwrei(); - int readIntrFlag(); - void setIntrFlag(int val); bool inPalMode(); void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 9d42ab05b..d86f2dc8b 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -260,20 +260,6 @@ OzoneDynInst::hwrei() return NoFault; } -template -int -OzoneDynInst::readIntrFlag() -{ -return this->cpu->readIntrFlag(); -} - -template -void -OzoneDynInst::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - template bool OzoneDynInst::inPalMode() -- cgit v1.2.3 From bfd5eb2b08dad700d085a637d5e16a61dcc530d7 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 31 Oct 2006 14:33:56 -0500 Subject: Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3 --- src/cpu/ozone/cpu.hh | 2 -- src/cpu/ozone/cpu_builder.cc | 5 ----- src/cpu/ozone/cpu_impl.hh | 19 +++---------------- src/cpu/ozone/front_end.hh | 2 -- src/cpu/ozone/front_end_impl.hh | 1 - src/cpu/ozone/lw_lsq.hh | 2 -- src/cpu/ozone/lw_lsq_impl.hh | 2 -- src/cpu/ozone/simple_params.hh | 2 -- src/cpu/ozone/thread_state.hh | 6 +++--- 9 files changed, 6 insertions(+), 35 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 70ec1d101..28ff8e9ba 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -368,8 +368,6 @@ class OzoneCPU : public BaseCPU virtual Port *getPort(const std::string &name, int idx); - MemObject *mem; - FrontEnd *frontEnd; BackEnd *backEnd; diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 730158258..39be9fd74 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -69,8 +69,6 @@ SimObjectVectorParam workload; //SimObjectParam page_table; #endif // FULL_SYSTEM -SimObjectParam mem; - SimObjectParam checker; Param max_insts_any_thread; @@ -191,8 +189,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) // INIT_PARAM(page_table, "Page table"), #endif // FULL_SYSTEM - INIT_PARAM_DFLT(mem, "Memory", NULL), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -350,7 +346,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) // params->pTable = page_table; #endif // FULL_SYSTEM - params->mem = mem; params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; params->max_insts_all_threads = max_insts_all_threads; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index bf547bf94..685bf3cb4 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -93,10 +93,10 @@ OzoneCPU::OzoneCPU(Params *p) #if FULL_SYSTEM : BaseCPU(p), thread(this, 0), tickEvent(this, p->width), #else - : BaseCPU(p), thread(this, 0, p->workload[0], 0, p->mem), + : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width), #endif - mem(p->mem), comm(5, 5) + comm(5, 5) { frontEnd = new FrontEnd(p); backEnd = new BackEnd(p); @@ -107,7 +107,6 @@ OzoneCPU::OzoneCPU(Params *p) #if USE_CHECKER BaseCPU *temp_checker = p->checker; checker = dynamic_cast *>(temp_checker); - checker->setMemory(mem); #if FULL_SYSTEM checker->setSystem(p->system); #endif @@ -198,19 +197,7 @@ OzoneCPU::OzoneCPU(Params *p) frontEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable); -#if !FULL_SYSTEM - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), 0), - p->workload[0]->pTable, - false); - mem_port = p->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - thread.setMemPort(trans_port); -#else +#if FULL_SYSTEM Port *mem_port; FunctionalPort *phys_port; VirtualPort *virt_port; diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index 2bdca35b9..e09e4de9c 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -208,8 +208,6 @@ class FrontEnd IcachePort icachePort; - MemObject *mem; - RequestPtr memReq; /** Mask to get a cache block's address. */ diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 36e87ec9c..b8fce4292 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -91,7 +91,6 @@ template FrontEnd::FrontEnd(Params *params) : branchPred(params), icachePort(this), - mem(params->mem), numInstsReady(params->frontEndLatency, 0), instBufferSize(0), maxInstBufferSize(params->maxInstBufferSize), diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index dc58a8285..7e6849668 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -239,8 +239,6 @@ class OzoneLWLSQ { /** Pointer to the back-end stage. */ BackEnd *be; - MemObject *mem; - class DcachePort : public Port { protected: diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 1f3f18502..ee1968626 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -154,8 +154,6 @@ OzoneLWLSQ::init(Params *params, unsigned maxLQEntries, SQIndices.push(i); } - mem = params->mem; - usedPorts = 0; cachePorts = params->cachePorts; diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh index 3f63d2e1d..3e554c812 100644 --- a/src/cpu/ozone/simple_params.hh +++ b/src/cpu/ozone/simple_params.hh @@ -61,8 +61,6 @@ class SimpleParams : public BaseCPU::Params //Page Table PageTable *pTable; - MemObject *mem; - // // Caches // diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index c86f3552e..c226d7502 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -67,7 +67,7 @@ struct OzoneThreadState : public ThreadState { #if FULL_SYSTEM OzoneThreadState(CPUType *_cpu, int _thread_num) - : ThreadState(-1, _thread_num), + : ThreadState(_cpu, -1, _thread_num), intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0) { if (cpu->params->profile) { @@ -87,8 +87,8 @@ struct OzoneThreadState : public ThreadState { } #else OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process, - int _asid, MemObject *mem) - : ThreadState(-1, _thread_num, _process, _asid, mem), + int _asid) + : ThreadState(_cpu, -1, _thread_num, _process, _asid), cpu(_cpu), inSyscall(0), trapPending(0) { miscRegFile.clear(); -- cgit v1.2.3 From 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Nov 2006 16:44:45 -0500 Subject: Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675 --- src/cpu/ozone/checker_builder.cc | 4 ++-- src/cpu/ozone/cpu.hh | 17 ++++++++++------- src/cpu/ozone/cpu_builder.cc | 4 ++-- src/cpu/ozone/cpu_impl.hh | 18 ++++++------------ src/cpu/ozone/dyn_inst.hh | 6 +++--- src/cpu/ozone/dyn_inst_impl.hh | 12 ++++++------ src/cpu/ozone/simple_cpu_builder.cc | 4 ++-- src/cpu/ozone/simple_params.hh | 9 ++++++--- src/cpu/ozone/thread_state.hh | 10 +++++----- 9 files changed, 42 insertions(+), 42 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index b4c4686b7..9ad1e639f 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -68,8 +68,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param progress_interval; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; SimObjectParam system; Param cpu_id; Param profile; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index bd46b198b..14c32620b 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -51,8 +51,11 @@ #if FULL_SYSTEM #include "arch/alpha/tlb.hh" -class AlphaITB; -class AlphaDTB; +namespace TheISA +{ + class ITB; + class DTB; +} class PhysicalMemory; class MemoryController; @@ -120,9 +123,9 @@ class OzoneCPU : public BaseCPU PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } - AlphaITB *getITBPtr() { return cpu->itb; } + TheISA::ITB *getITBPtr() { return cpu->itb; } - AlphaDTB * getDTBPtr() { return cpu->dtb; } + TheISA::DTB * getDTBPtr() { return cpu->dtb; } Kernel::Statistics *getKernelStats() { return thread->getKernelStats(); } @@ -224,11 +227,11 @@ class OzoneCPU : public BaseCPU // ISA stuff: MiscReg readMiscReg(int misc_reg); - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); + MiscReg readMiscRegWithEffect(int misc_reg); - Fault setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val); unsigned readStCondFailures() { return thread->storeCondFailures; } diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 730158258..8a572ba38 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -61,8 +61,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU) #if FULL_SYSTEM SimObjectParam system; Param cpu_id; -SimObjectParam itb; -SimObjectParam dtb; +SimObjectParam itb; +SimObjectParam dtb; Param profile; #else SimObjectVectorParam workload; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index bf547bf94..b34b061d9 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -1156,37 +1156,31 @@ OzoneCPU::OzoneTC::readMiscReg(int misc_reg) template TheISA::MiscReg -OzoneCPU::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault) +OzoneCPU::OzoneTC::readMiscRegWithEffect(int misc_reg) { - return thread->miscRegFile.readRegWithEffect(misc_reg, - fault, this); + return thread->miscRegFile.readRegWithEffect(misc_reg, this); } template -Fault +void OzoneCPU::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode - Fault ret_fault = thread->miscRegFile.setReg(misc_reg, val); + thread->miscRegFile.setReg(misc_reg, val); if (!thread->inSyscall) { cpu->squashFromTC(); } - - return ret_fault; } template -Fault +void OzoneCPU::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode - Fault ret_fault = thread->miscRegFile.setRegWithEffect(misc_reg, val, - this); + thread->miscRegFile.setRegWithEffect(misc_reg, val, this); if (!thread->inSyscall) { cpu->squashFromTC(); } - - return ret_fault; } diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index d3871568a..532317b08 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -230,11 +230,11 @@ class OzoneDynInst : public BaseDynInst // ISA stuff MiscReg readMiscReg(int misc_reg); - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); + MiscReg readMiscRegWithEffect(int misc_reg); - Fault setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val); #if FULL_SYSTEM Fault hwrei(); diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index d86f2dc8b..68736ae61 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -223,24 +223,24 @@ OzoneDynInst::readMiscReg(int misc_reg) template TheISA::MiscReg -OzoneDynInst::readMiscRegWithEffect(int misc_reg, Fault &fault) +OzoneDynInst::readMiscRegWithEffect(int misc_reg) { - return this->thread->readMiscRegWithEffect(misc_reg, fault); + return this->thread->readMiscRegWithEffect(misc_reg); } template -Fault +void OzoneDynInst::setMiscReg(int misc_reg, const MiscReg &val) { this->setIntResult(val); - return this->thread->setMiscReg(misc_reg, val); + this->thread->setMiscReg(misc_reg, val); } template -Fault +void OzoneDynInst::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return this->thread->setMiscRegWithEffect(misc_reg, val); + this->thread->setMiscRegWithEffect(misc_reg, val); } #if FULL_SYSTEM diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc index baaf7c708..e7214d2ba 100644 --- a/src/cpu/ozone/simple_cpu_builder.cc +++ b/src/cpu/ozone/simple_cpu_builder.cc @@ -64,8 +64,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU) #if FULL_SYSTEM SimObjectParam system; Param cpu_id; -SimObjectParam itb; -SimObjectParam dtb; +SimObjectParam itb; +SimObjectParam dtb; #else SimObjectVectorParam workload; //SimObjectParam page_table; diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh index 3f63d2e1d..3473b088c 100644 --- a/src/cpu/ozone/simple_params.hh +++ b/src/cpu/ozone/simple_params.hh @@ -34,8 +34,11 @@ #include "cpu/ozone/cpu.hh" //Forward declarations -class AlphaDTB; -class AlphaITB; +namespace TheISA +{ + class DTB; + class ITB; +} class FUPool; class MemObject; class PageTable; @@ -53,7 +56,7 @@ class SimpleParams : public BaseCPU::Params public: #if FULL_SYSTEM - AlphaITB *itb; AlphaDTB *dtb; + TheISA::ITB *itb; TheISA::DTB *dtb; #else std::vector workload; #endif // FULL_SYSTEM diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index 985e09b52..ec51251b7 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -120,19 +120,19 @@ struct OzoneThreadState : public ThreadState { return miscRegFile.readReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { return miscRegFile.readRegWithEffect(misc_reg, fault, tc); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { - return miscRegFile.setReg(misc_reg, val); + miscRegFile.setReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return miscRegFile.setRegWithEffect(misc_reg, val, tc); + miscRegFile.setRegWithEffect(misc_reg, val, tc); } uint64_t readPC() -- cgit v1.2.3 From ccaf80cc46fb86639ab5ee166baca08277f5450f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 2 Nov 2006 13:11:38 -0500 Subject: Use ISA specific makeExtMI. src/arch/alpha/utility.hh: For now makeExtMI will be specific to the ISA. --HG-- extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496 --- src/cpu/ozone/front_end_impl.hh | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 63cf0a952..6d02c58cb 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -882,7 +882,11 @@ FrontEnd::getInstFromCacheline() // Get the instruction from the array of the cache line. inst = htog(*reinterpret_cast(&cacheData[offset])); +#if THE_ISA == ALPHA_ISA + ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC); +#elif THE_ISA == SPARC_ISA ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc); +#endif // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst), -- cgit v1.2.3 From 118b9dc1f9e84a12ea26743f6cec1eac5b4ab13a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 04:25:33 -0500 Subject: Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however. --HG-- extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b --- src/cpu/ozone/cpu.hh | 6 ------ src/cpu/ozone/dyn_inst.hh | 1 - src/cpu/ozone/dyn_inst_impl.hh | 9 +-------- src/cpu/ozone/front_end_impl.hh | 9 ++------- src/cpu/ozone/inorder_back_end_impl.hh | 6 +++--- src/cpu/ozone/lw_back_end_impl.hh | 3 +-- 6 files changed, 7 insertions(+), 27 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 828c2b4ca..b3d3531e9 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -239,10 +239,6 @@ class OzoneCPU : public BaseCPU void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; } -#if FULL_SYSTEM - bool inPalMode() { return cpu->inPalMode(); } -#endif - bool misspeculating() { return false; } #if !FULL_SYSTEM @@ -584,8 +580,6 @@ class OzoneCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei(); - bool inPalMode() { return AlphaISA::PcPAL(thread.PC); } - bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); } bool simPalCheck(int palFunc); void processInterrupts(); #else diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index 532317b08..9445a5309 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -238,7 +238,6 @@ class OzoneDynInst : public BaseDynInst #if FULL_SYSTEM Fault hwrei(); - bool inPalMode(); void trap(Fault fault); bool simPalCheck(int palFunc); #else diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 68736ae61..426841536 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -249,7 +249,7 @@ template Fault OzoneDynInst::hwrei() { - if (!this->cpu->inPalMode(this->readPC())) + if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR)); @@ -260,13 +260,6 @@ OzoneDynInst::hwrei() return NoFault; } -template -bool -OzoneDynInst::inPalMode() -{ - return this->cpu->inPalMode(); -} - template void OzoneDynInst::trap(Fault fault) diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 6d02c58cb..73ca6afbe 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -462,15 +462,10 @@ Fault FrontEnd::fetchCacheLine() { // Read a cache line, based on the current PC. -#if FULL_SYSTEM - // Flag to say whether or not address is physical addr. - unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0; -#else - unsigned flags = 0; -#endif // FULL_SYSTEM Fault fault = NoFault; - if (interruptPending && flags == 0) { + //AlphaDep + if (interruptPending && (PC & 0x3)) { return fault; } diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 8aef9c074..87bf0a7a2 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -152,11 +152,11 @@ InorderBackEnd::tick() #if FULL_SYSTEM if (interruptBlocked || (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode())) { + cpu->check_interrupts(tc))) { if (!robEmpty()) { interruptBlocked = true; - } else if (robEmpty() && cpu->inPalMode()) { + //AlphaDep + } else if (robEmpty() && (PC & 0x3)) { // Will need to let the front end continue a bit until // we're out of pal mode. Hopefully we never get into an // infinite loop... diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index c39b9e08b..a181c93f4 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -526,8 +526,7 @@ void LWBackEnd::checkInterrupts() { if (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode(thread->readPC()) && + cpu->check_interrupts(tc) && !trapSquash && !tcSquash) { frontEnd->interruptPending = true; -- cgit v1.2.3 From 4bfb8547bbdee3bd0ec23ae067ff04fd5e07f4be Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:36:54 -0500 Subject: Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats --HG-- extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017 --- src/cpu/ozone/cpu.hh | 8 +++++--- src/cpu/ozone/cpu_impl.hh | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index b3d3531e9..2b2ed7b3e 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -62,8 +62,10 @@ class MemoryController; class RemoteGDB; class GDBListener; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; #else @@ -127,7 +129,7 @@ class OzoneCPU : public BaseCPU TheISA::DTB * getDTBPtr() { return cpu->dtb; } - Kernel::Statistics *getKernelStats() + TheISA::Kernel::Statistics *getKernelStats() { return thread->getKernelStats(); } FunctionalPort *getPhysPort() { return thread->getPhysPort(); } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 6f5dede3e..b83cf4e9e 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -891,7 +891,7 @@ void OzoneCPU::OzoneTC::regStats(const std::string &name) { #if FULL_SYSTEM - thread->kernelStats = new Kernel::Statistics(cpu->system); + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats->regStats(name + ".kern"); #endif } -- cgit v1.2.3 From 4589ec55aed596a4b0b7d81779f2b4665643d223 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Nov 2006 13:53:49 -0500 Subject: Fix compile error. --HG-- extra : convert_revision : a4c4195bc07383149a56907f26d327a4bfa77c26 --- src/cpu/ozone/cpu.hh | 4 ++-- src/cpu/ozone/thread_state.hh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 828c2b4ca..ccb467394 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -363,8 +363,8 @@ class OzoneCPU : public BaseCPU bool interval_stats; - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; System *system; PhysicalMemory *physmem; #endif diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index c4d16b3af..a71795851 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState { MiscReg readMiscRegWithEffect(int misc_reg) { - return miscRegFile.readRegWithEffect(misc_reg, fault, tc); + return miscRegFile.readRegWithEffect(misc_reg, tc); } void setMiscReg(int misc_reg, const MiscReg &val) -- cgit v1.2.3 From c693c6ba9f9d641344db8a2a505484f5f8aa2645 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 22:34:34 -0500 Subject: Put kernel_stats back into arch. --HG-- rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966 --- src/cpu/ozone/cpu_impl.hh | 6 +++--- src/cpu/ozone/dyn_inst_impl.hh | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src/cpu/ozone') diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index b83cf4e9e..86c973a0f 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -47,12 +47,12 @@ #if FULL_SYSTEM #include "arch/faults.hh" #include "arch/alpha/osfpal.hh" -#include "arch/alpha/tlb.hh" -#include "arch/alpha/types.hh" +#include "arch/tlb.hh" +#include "arch/types.hh" +#include "arch/kernel_stats.hh" #include "arch/vtophys.hh" #include "base/callback.hh" #include "cpu/profile.hh" -#include "kern/kernel_stats.hh" #include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 426841536..05a66d77a 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -31,7 +31,10 @@ #include "sim/faults.hh" #include "config/full_system.hh" #include "cpu/ozone/dyn_inst.hh" + +#if FULL_SYSTEM #include "kern/kernel_stats.hh" +#endif template OzoneDynInst::OzoneDynInst(OzoneCPU *cpu) -- cgit v1.2.3