From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/cpu/reg_class.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/cpu/reg_class.cc')

diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index a3de17b8b..1805eae13 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -33,5 +33,6 @@
 const char *RegClassStrings[] = {
     "IntRegClass",
     "FloatRegClass",
+    "CCRegClass",
     "MiscRegClass"
 };
-- 
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