From ec4000e0e284834df0eb1db792074a1b11f21cc8 Mon Sep 17 00:00:00 2001 From: Vincentius Robby Date: Wed, 8 Aug 2007 18:43:12 -0400 Subject: Added fastmem option. Lets CPU accesses to physical memory bypass Bus. --HG-- extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c --- src/cpu/simple/AtomicSimpleCPU.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/cpu/simple/AtomicSimpleCPU.py') diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index e97f059c1..bfd1825c2 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + physmem_port = Port("Physical Memory Port") + _mem_ports = ['icache_port', 'dcache_port', 'physmem_port'] -- cgit v1.2.3