From c0d613adb4eca09c32aca1cc90f04c29574f69c6 Mon Sep 17 00:00:00 2001 From: Anouk Van Laer Date: Fri, 17 Mar 2017 12:02:00 +0000 Subject: pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg --- src/cpu/simple/atomic.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/cpu/simple/atomic.cc') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index c47686abc..9039e6137 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -1,6 +1,6 @@ /* * Copyright 2014 Google, Inc. - * Copyright (c) 2012-2013,2015 ARM Limited + * Copyright (c) 2012-2013,2015,2017 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -101,6 +101,9 @@ AtomicSimpleCPU::~AtomicSimpleCPU() DrainState AtomicSimpleCPU::drain() { + // Deschedule any power gating event (if any) + deschedulePowerGatingEvent(); + if (switchedOut()) return DrainState::Drained; @@ -163,6 +166,9 @@ AtomicSimpleCPU::drainResume() threadInfo[tid]->notIdleFraction = 0; } } + + // Reschedule any power gating event (if any) + schedulePowerGatingEvent(); } bool -- cgit v1.2.3