From e0de2c34433be76eac7798e58e1ae02f5bffb732 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 8 Apr 2009 22:21:27 -0700 Subject: tlb: More fixing of unified TLB --- src/cpu/simple/atomic.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/cpu/simple/atomic.cc') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index b5e65265a..601111588 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) req->setVirt(0, addr, dataSize, flags, thread->readPC()); // translate to physical address - Fault fault = thread->dtb->translateAtomic(req, tc, false); + Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); // Now do the access. if (fault == NoFault) { @@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) req->setVirt(0, addr, dataSize, flags, thread->readPC()); // translate to physical address - Fault fault = thread->dtb->translateAtomic(req, tc, true); + Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); // Now do the access. if (fault == NoFault) { @@ -609,7 +609,8 @@ AtomicSimpleCPU::tick() bool fromRom = isRomMicroPC(thread->readMicroPC()); if (!fromRom && !curMacroStaticInst) { setupFetchRequest(&ifetch_req); - fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true); + fault = thread->itb->translateAtomic(&ifetch_req, tc, + BaseTLB::Execute); } if (fault == NoFault) { -- cgit v1.2.3