From ca3513d63038e562782cd193c00c3892a276bb5d Mon Sep 17 00:00:00 2001
From: Dam Sunwoo <dam.sunwoo@arm.com>
Date: Sat, 20 Sep 2014 17:17:43 -0400
Subject: cpu: use probes infrastructure to do simpoint profiling

Instead of having code embedded in cpu model to do simpoint profiling use
the probes infrastructure to do it.
---
 src/cpu/simple/atomic.hh | 70 ++++--------------------------------------------
 1 file changed, 5 insertions(+), 65 deletions(-)

(limited to 'src/cpu/simple/atomic.hh')

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 7426139e7..91f558e06 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -43,30 +43,9 @@
 #ifndef __CPU_SIMPLE_ATOMIC_HH__
 #define __CPU_SIMPLE_ATOMIC_HH__
 
-#include "base/hashmap.hh"
 #include "cpu/simple/base.hh"
 #include "params/AtomicSimpleCPU.hh"
-
-/**
- *  Start and end address of basic block for SimPoint profiling.
- *  This structure is used to look up the hash table of BBVs.
- *  - first: PC of first inst in basic block
- *  - second: PC of last inst in basic block
- */
-typedef std::pair<Addr, Addr> BasicBlockRange;
-
-/** Overload hash function for BasicBlockRange type */
-__hash_namespace_begin
-template <>
-struct hash<BasicBlockRange>
-{
-  public:
-    size_t operator()(const BasicBlockRange &bb) const {
-        return hash<Addr>()(bb.first + bb.second);
-    }
-};
-__hash_namespace_end
-
+#include "sim/probe/probe.hh"
 
 class AtomicSimpleCPU : public BaseSimpleCPU
 {
@@ -200,49 +179,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     bool dcache_access;
     Tick dcache_latency;
 
-    /**
-     * Profile basic blocks for SimPoints.
-     * Called at every macro inst to increment basic block inst counts and
-     * to profile block if end of block.
-     */
-    void profileSimPoint();
-
-    /** Data structures for SimPoints BBV generation
-     *  @{
-     */
-
-    /** Whether SimPoint BBV profiling is enabled */
-    const bool simpoint;
-    /** SimPoint profiling interval size in instructions */
-    const uint64_t intervalSize;
-
-    /** Inst count in current basic block */
-    uint64_t intervalCount;
-    /** Excess inst count from previous interval*/
-    uint64_t intervalDrift;
-    /** Pointer to SimPoint BBV output stream */
-    std::ostream *simpointStream;
-
-    /** Basic Block information */
-    struct BBInfo {
-        /** Unique ID */
-        uint64_t id;
-        /** Num of static insts in BB */
-        uint64_t insts;
-        /** Accumulated dynamic inst count executed by BB */
-        uint64_t count;
-    };
-
-    /** Hash table containing all previously seen basic blocks */
-    m5::hash_map<BasicBlockRange, BBInfo> bbMap;
-    /** Currently executing basic block */
-    BasicBlockRange currentBBV;
-    /** inst count in current basic block */
-    uint64_t currentBBVInstCount;
-
-    /** @}
-     *  End of data structures for SimPoints BBV generation
-     */
+    /** Probe Points. */
+    ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
 
   protected:
 
@@ -270,6 +208,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     Fault writeMem(uint8_t *data, unsigned size,
                    Addr addr, unsigned flags, uint64_t *res);
 
+    virtual void regProbePoints();
+
     /**
      * Print state of address in memory system via PrintReq (for
      * debugging).
-- 
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