From 269259004943b80916ec9b6354f2fc00c811c88b Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 13 Nov 2007 16:58:16 -0500
Subject: Add in files from merge-bare-iron, get them compiling in FS and SE
 mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
---
 src/cpu/simple/base.cc | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

(limited to 'src/cpu/simple/base.cc')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 1611a7275..e521837df 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -503,3 +503,37 @@ BaseSimpleCPU::advancePC(Fault fault)
     } while (oldpc != thread->readPC());
 }
 
+Fault
+BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
+{
+    // translate to physical address
+    Fault fault = NoFault;
+    int CacheID = Op & 0x3; // Lower 3 bits identify Cache
+    int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
+    if(CacheID > 1)
+      {
+        warn("CacheOps not implemented for secondary/tertiary caches\n");
+      }
+    else
+      {
+        switch(CacheOP)
+          { // Fill Packet Type
+          case 0: warn("Invalidate Cache Op\n");
+            break;
+          case 1: warn("Index Load Tag Cache Op\n");
+            break;
+          case 2: warn("Index Store Tag Cache Op\n");
+            break;
+          case 4: warn("Hit Invalidate Cache Op\n");
+            break;
+          case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
+            break;
+          case 6: warn("Hit Writeback\n");
+            break;
+          case 7: warn("Fetch & Lock Cache Op\n");
+            break;
+          default: warn("Unimplemented Cache Op\n");
+          }
+      }
+    return fault;
+}
-- 
cgit v1.2.3