From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001 From: Yasuko Eckert Date: Tue, 15 Oct 2013 14:22:44 -0400 Subject: cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. --- src/cpu/simple/base.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/cpu/simple/base.cc') diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 012a49253..078f490e8 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -211,6 +212,18 @@ BaseSimpleCPU::regStats() .desc("number of times the floating registers were written") ; + numCCRegReads + .name(name() + ".num_cc_register_reads") + .desc("number of times the CC registers were read") + .flags(nozero) + ; + + numCCRegWrites + .name(name() + ".num_cc_register_writes") + .desc("number of times the CC registers were written") + .flags(nozero) + ; + numMemRefs .name(name()+".num_mem_refs") .desc("number of memory refs") -- cgit v1.2.3