From c0d613adb4eca09c32aca1cc90f04c29574f69c6 Mon Sep 17 00:00:00 2001 From: Anouk Van Laer Date: Fri, 17 Mar 2017 12:02:00 +0000 Subject: pwr: Adds logic to enter power gating for the cpu model If the CPU has been clock gated for a sufficient amount of time (configurable via pwrGatingLatency), the CPU will go into the OFF power state. This does not model hardware, just behaviour. Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43 Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/3969 Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg --- src/cpu/simple/timing.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/cpu/simple/timing.cc') diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index d2cb6ee21..f57354d56 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1,6 +1,6 @@ /* * Copyright 2014 Google, Inc. - * Copyright (c) 2010-2013,2015 ARM Limited + * Copyright (c) 2010-2013,2015,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -94,6 +94,9 @@ TimingSimpleCPU::~TimingSimpleCPU() DrainState TimingSimpleCPU::drain() { + // Deschedule any power gating event (if any) + deschedulePowerGatingEvent(); + if (switchedOut()) return DrainState::Drained; @@ -146,6 +149,9 @@ TimingSimpleCPU::drainResume() } } + // Reschedule any power gating event (if any) + schedulePowerGatingEvent(); + system->totalNumInsts = 0; } -- cgit v1.2.3