From f17f3d20be08d25f176138691a29897df54e5cc0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:24 -0800 Subject: X86: Implement a page table walker. --HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec --- src/cpu/simple/AtomicSimpleCPU.py | 3 ++- src/cpu/simple/TimingSimpleCPU.py | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index bfd1825c2..28c2aa9c9 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -41,4 +41,5 @@ class AtomicSimpleCPU(BaseCPU): icache_port = Port("Instruction Port") dcache_port = Port("Data Port") physmem_port = Port("Physical Memory Port") - _mem_ports = ['icache_port', 'dcache_port', 'physmem_port'] + _mem_ports = BaseCPU._mem_ports + \ + ['icache_port', 'dcache_port', 'physmem_port'] diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 2fcde175c..7e777e813 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port'] -- cgit v1.2.3 From fce45baf178b43c2ea1476967fba3766e9b2ea9d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:31 -0800 Subject: X86: Work on the page table walker, TLB, and related faults. --HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f --- src/cpu/simple/base.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 1611a7275..98e29d8d1 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault) if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; predecoder.reset(); - fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); + fault->invoke(tc); } else { //If we're at the last micro op for this instruction if (curStaticInst && curStaticInst->isLastMicroop()) { -- cgit v1.2.3