From 4862879a9420c52d48532d957b616c458b643a1e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 02:08:44 -0500 Subject: Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names. --HG-- extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4 --- src/cpu/simple/atomic.cc | 4 ++-- src/cpu/simple/base.hh | 11 +++++++---- src/cpu/simple/timing.cc | 4 ++-- 3 files changed, 11 insertions(+), 8 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 11e4d2acb..1e12aadef 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -513,8 +513,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) Param cpu_id; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; Param profile; #else SimObjectParam workload; diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index af6b6f835..1a9fc5127 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -47,8 +47,11 @@ // forward declarations #if FULL_SYSTEM class Processor; -class AlphaITB; -class AlphaDTB; +namespace TheISA +{ + class ITB; + class DTB; +} class MemObject; class RemoteGDB; @@ -97,8 +100,8 @@ class BaseSimpleCPU : public BaseCPU { MemObject *mem; #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #else Process *process; #endif diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fe6775ea4..438417882 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -665,8 +665,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) Param cpu_id; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; Param profile; #else SimObjectParam workload; -- cgit v1.2.3