From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001
From: Nathanael Premillieu <nathanael.premillieu@arm.com>
Date: Wed, 5 Apr 2017 12:46:06 -0500
Subject: arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
---
 src/cpu/simple/exec_context.hh | 53 ++++++++++++++++++++++++++----------------
 1 file changed, 33 insertions(+), 20 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index bfae118ad..9689796f3 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -50,6 +50,7 @@
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/simple/base.hh"
 #include "cpu/static_inst_fwd.hh"
 #include "cpu/translation.hh"
@@ -164,22 +165,27 @@ class SimpleExecContext : public ExecContext {
     IntReg readIntRegOperand(const StaticInst *si, int idx) override
     {
         numIntRegReads++;
-        return thread->readIntReg(si->srcRegIdx(idx));
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == IntRegClass);
+        return thread->readIntReg(reg.regIdx);
     }
 
     /** Sets an integer register to a value. */
     void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
     {
         numIntRegWrites++;
-        thread->setIntReg(si->destRegIdx(idx), val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == IntRegClass);
+        thread->setIntReg(reg.regIdx, val);
     }
 
     /** Reads a floating point register of single register width. */
     FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
     {
         numFpRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
-        return thread->readFloatReg(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        return thread->readFloatReg(reg.regIdx);
     }
 
     /** Reads a floating point register in its binary format, instead
@@ -187,8 +193,9 @@ class SimpleExecContext : public ExecContext {
     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
     {
         numFpRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
-        return thread->readFloatRegBits(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        return thread->readFloatRegBits(reg.regIdx);
     }
 
     /** Sets a floating point register of single width to a value. */
@@ -196,8 +203,9 @@ class SimpleExecContext : public ExecContext {
                             FloatReg val) override
     {
         numFpRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
-        thread->setFloatReg(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        thread->setFloatReg(reg.regIdx, val);
     }
 
     /** Sets the bits of a floating point register of single width
@@ -206,37 +214,42 @@ class SimpleExecContext : public ExecContext {
                                 FloatRegBits val) override
     {
         numFpRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
-        thread->setFloatRegBits(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        thread->setFloatRegBits(reg.regIdx, val);
     }
 
     CCReg readCCRegOperand(const StaticInst *si, int idx) override
     {
         numCCRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
-        return thread->readCCReg(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == CCRegClass);
+        return thread->readCCReg(reg.regIdx);
     }
 
     void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
     {
         numCCRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
-        thread->setCCReg(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == CCRegClass);
+        thread->setCCReg(reg.regIdx, val);
     }
 
     MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
     {
         numIntRegReads++;
-        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
-        return thread->readMiscReg(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == MiscRegClass);
+        return thread->readMiscReg(reg.regIdx);
     }
 
     void setMiscRegOperand(const StaticInst *si, int idx,
                            const MiscReg &val) override
     {
         numIntRegWrites++;
-        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
-        thread->setMiscReg(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == MiscRegClass);
+        thread->setMiscReg(reg.regIdx, val);
     }
 
     /**
@@ -398,14 +411,14 @@ class SimpleExecContext : public ExecContext {
     }
 
 #if THE_ISA == MIPS_ISA
-    MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
+    MiscReg readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID)
         override
     {
         panic("Simple CPU models do not support multithreaded "
               "register access.");
     }
 
-    void setRegOtherThread(int regIdx, MiscReg val,
+    void setRegOtherThread(RegId reg, MiscReg val,
                            ThreadID tid = InvalidThreadID) override
     {
         panic("Simple CPU models do not support multithreaded "
-- 
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