From 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 19 Nov 2018 18:14:16 -0800 Subject: arch: cpu: Rename *FloatRegBits* to *FloatReg*. Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black --- src/cpu/simple/base.cc | 2 +- src/cpu/simple/exec_context.hh | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index c597ac904..f71277d1c 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -493,7 +493,7 @@ BaseSimpleCPU::preExecute() // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatRegBits(ZeroReg, 0); + thread->setFloatReg(ZeroReg, 0); #endif // ALPHA_ISA // check for instruction-count-based events diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index d2107b89a..3090f38a0 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -202,7 +202,7 @@ class SimpleExecContext : public ExecContext { numFpRegReads++; const RegId& reg = si->srcRegIdx(idx); assert(reg.isFloatReg()); - return thread->readFloatRegBits(reg.index()); + return thread->readFloatReg(reg.index()); } /** Sets the bits of a floating point register of single width @@ -213,7 +213,7 @@ class SimpleExecContext : public ExecContext { numFpRegWrites++; const RegId& reg = si->destRegIdx(idx); assert(reg.isFloatReg()); - thread->setFloatRegBits(reg.index(), val); + thread->setFloatReg(reg.index(), val); } /** Reads a vector register. */ -- cgit v1.2.3