From 7227ab5f223eb5f4d3ce80ea16bff5f87c3300b6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 26 Aug 2007 21:45:40 -0700 Subject: Merge with head --HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6 --- src/cpu/simple/atomic.cc | 2 ++ src/cpu/simple/timing.cc | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 234803be5..06f52e30e 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -328,6 +328,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) dcache_latency += dcachePort.sendAtomic(&pkt); } dcache_access = true; + assert(!pkt.isError()); if (req->isLocked()) { @@ -611,6 +612,7 @@ AtomicSimpleCPU::tick() else icache_latency = icachePort.sendAtomic(&ifetch_pkt); + assert(!ifetch_pkt.isError()); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 1e1f43f7d..8d1cf9a17 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -583,7 +583,7 @@ TimingSimpleCPU::IcachePort::ITickEvent::process() bool TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) { - if (pkt->isResponse()) { + if (pkt->isResponse() && !pkt->wasNacked()) { // delay processing of returned data until next CPU clock edge Tick next_tick = cpu->nextCycle(curTick); @@ -686,7 +686,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port) bool TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) { - if (pkt->isResponse()) { + if (pkt->isResponse() && !pkt->wasNacked()) { // delay processing of returned data until next CPU clock edge Tick next_tick = cpu->nextCycle(curTick); -- cgit v1.2.3