From 8d018aef0f9de7129a77172a4164f36b2b093be6 Mon Sep 17 00:00:00 2001 From: Richard Strong Date: Mon, 18 Aug 2008 10:50:58 -0700 Subject: Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes. --- src/cpu/simple/AtomicSimpleCPU.py | 2 -- src/cpu/simple/TimingSimpleCPU.py | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index e1c1e4cd1..87e8b5509 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -37,8 +37,6 @@ class AtomicSimpleCPU(BaseSimpleCPU): simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") - if build_env['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") physmem_port = Port("Physical Memory Port") diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index f2b14a175..b7f044bfa 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -34,8 +34,6 @@ class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") - if build_env['FULL_SYSTEM']: - profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port'] -- cgit v1.2.3