From a119a963240a35ab66a5baee3f77cfcd99c6bbbb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 21 Nov 2018 16:20:57 -0800 Subject: cpu, arch: Replace the CCReg type with RegVal. Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/cpu/simple/exec_context.hh | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 3090f38a0..0552dc0c6 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -60,7 +60,6 @@ class BaseSimpleCPU; class SimpleExecContext : public ExecContext { protected: - typedef TheISA::CCReg CCReg; using VecRegContainer = TheISA::VecRegContainer; using VecElem = TheISA::VecElem; @@ -365,7 +364,7 @@ class SimpleExecContext : public ExecContext { thread->setVecPredReg(reg, val); } - CCReg + RegVal readCCRegOperand(const StaticInst *si, int idx) override { numCCRegReads++; @@ -375,7 +374,7 @@ class SimpleExecContext : public ExecContext { } void - setCCRegOperand(const StaticInst *si, int idx, CCReg val) override + setCCRegOperand(const StaticInst *si, int idx, RegVal val) override { numCCRegWrites++; const RegId& reg = si->destRegIdx(idx); -- cgit v1.2.3