From af7315c7dc20833a59044d1624d4fb9d71f1306f Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 9 Oct 2006 19:13:06 -0400
Subject: Fix caches plus sampling switch over.
src/cpu/o3/cpu.cc:
Fix up caches plus sampling switch over.
--HG--
extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
---
src/cpu/simple/timing.cc | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
(limited to 'src/cpu/simple')
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 015fdf8bc..9bed5dab1 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -191,9 +191,13 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
}
}
+ if (_status != Running) {
+ _status = Idle;
+ }
+
Port *peer;
if (icachePort.getPeer() == NULL) {
- peer = oldCPU->getPort("icachePort")->getPeer();
+ peer = oldCPU->getPort("icache_port")->getPeer();
icachePort.setPeer(peer);
} else {
peer = icachePort.getPeer();
@@ -201,7 +205,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
peer->setPeer(&icachePort);
if (dcachePort.getPeer() == NULL) {
- peer = oldCPU->getPort("dcachePort")->getPeer();
+ peer = oldCPU->getPort("dcache_port")->getPeer();
dcachePort.setPeer(peer);
} else {
peer = dcachePort.getPeer();
@@ -545,21 +549,20 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
numCycles += curTick - previousTick;
previousTick = curTick;
- if (getState() == SimObject::Draining) {
- completeDrain();
-
- delete pkt->req;
- delete pkt;
-
- return;
- }
-
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
delete pkt->req;
delete pkt;
postExecute();
+
+ if (getState() == SimObject::Draining) {
+ advancePC(fault);
+ completeDrain();
+
+ return;
+ }
+
advanceInst(fault);
}
--
cgit v1.2.3