From c55a467a06eaa59c47c52a2adddc266b8e545589 Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Sun, 2 Nov 2008 21:56:57 -0500
Subject: make BaseCPU the provider of _cpuId, and cpuId() instead of being
 scattered across the subclasses. generally make it so that member data is
 _cpuId and accessor functions are cpuId(). The ID val comes from the python
 (default -1 if none provided), and if it is -1, the index of cpuList will be
 given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well
 as standard switch.

---
 src/cpu/simple/atomic.cc | 16 +++++++---------
 src/cpu/simple/base.hh   |  1 -
 src/cpu/simple/timing.cc | 15 +++++++--------
 3 files changed, 14 insertions(+), 18 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 30f4a5c5e..5e8ab9443 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -79,13 +79,12 @@ void
 AtomicSimpleCPU::init()
 {
     BaseCPU::init();
-    cpuId = tc->readCpuId();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, cpuId);
+        TheISA::initCPU(tc, _cpuId);
     }
 #endif
     if (hasPhysMemPort) {
@@ -94,9 +93,9 @@ AtomicSimpleCPU::init()
         physmemPort.getPeerAddressRanges(pmAddrList, snoop);
         physMemAddr = *pmAddrList.begin();
     }
-    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
-    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
-    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
+    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
+    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
+    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
 }
 
 bool
@@ -237,10 +236,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    cpuId = tc->readCpuId();
-    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
-    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
-    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
+    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
+    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
+    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
 }
 
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index dc736c22e..6e72b8f6c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -121,7 +121,6 @@ class BaseSimpleCPU : public BaseCPU
      */
     ThreadContext *tc;
   protected:
-    int cpuId;
 
     enum Status {
         Idle,
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a6059f55f..247899ca8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -57,13 +57,12 @@ void
 TimingSimpleCPU::init()
 {
     BaseCPU::init();
-    cpuId = tc->readCpuId();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, cpuId);
+        TheISA::initCPU(tc, _cpuId);
     }
 #endif
 }
@@ -203,7 +202,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    cpuId = tc->readCpuId();
+    _cpuId = tc->cpuId();
     previousTick = curTick;
 }
 
@@ -250,7 +249,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    cpuId, /* thread ID */ 0);
+                    _cpuId, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -301,7 +300,7 @@ TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
         int size, unsigned flags)
 {
     Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
 
     if (traceData) {
         traceData->setAddr(vaddr);
@@ -373,7 +372,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    cpuId, /* thread ID */ 0);
+                    _cpuId, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -442,7 +441,7 @@ TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
         int size, unsigned flags)
 {
     Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
 
     if (traceData) {
         traceData->setAddr(vaddr);
@@ -528,7 +527,7 @@ TimingSimpleCPU::fetch()
 
     if (!fromRom) {
         Request *ifetch_req = new Request();
-        ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
+        ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         Fault fault = setupFetchRequest(ifetch_req);
 
         ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
-- 
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