From ca89eba79ebe0adc9cea7656c288e0381754171a Mon Sep 17 00:00:00 2001 From: Matt Horsnell Date: Fri, 24 Jan 2014 15:29:30 -0600 Subject: mem: track per-request latencies and access depths in the cache hierarchy Add some values and methods to the request object to track the translation and access latency for a request and which level of the cache hierarchy responded to the request. --- src/cpu/simple/timing.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 744bf8397..9253d8005 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -646,7 +646,6 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) // received a response from the icache: execute the received // instruction - assert(!pkt || !pkt->isError()); assert(_status == IcacheWaitResponse); @@ -655,6 +654,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) numCycles += curCycle() - previousCycle; previousCycle = curCycle(); + if (pkt) + pkt->req->setAccessLatency(); + + preExecute(); if (curStaticInst && curStaticInst->isMemRef()) { // load or store: just send to dcache @@ -749,6 +752,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) assert(_status == DcacheWaitResponse || _status == DTBWaitResponse || pkt->req->getFlags().isSet(Request::NO_ACCESS)); + pkt->req->setAccessLatency(); numCycles += curCycle() - previousCycle; previousCycle = curCycle(); -- cgit v1.2.3