From d093fcb07924cc4341b8142c448b905dd94f7125 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 12 Jun 2008 00:35:50 -0400
Subject: CPU: Make the simple cpu trace data for loads/stores.

---
 src/cpu/simple/atomic.cc | 6 ++++++
 src/cpu/simple/timing.cc | 6 ++++++
 2 files changed, 12 insertions(+)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 23bd40b9b..acd280568 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -355,6 +355,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         if (secondAddr <= addr)
         {
             data = gtoh(data);
+            if (traceData) {
+                traceData->setData(data);
+            }
             return fault;
         }
 
@@ -568,6 +571,9 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
             // If the write needs to have a fault on the access, consider
             // calling changeStatus() and changing it to "bad addr write"
             // or something.
+            if (traceData) {
+                traceData->setData(data);
+            }
             return fault;
         }
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a76824ff3..d0c7dd787 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -296,6 +296,9 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
         delete req;
     }
 
+    if (traceData) {
+        traceData->setData(data);
+    }
     return fault;
 }
 
@@ -431,6 +434,9 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         delete req;
     }
 
+    if (traceData) {
+        traceData->setData(data);
+    }
 
     // If the write needs to have a fault on the access, consider calling
     // changeStatus() and changing it to "bad addr write" or something.
-- 
cgit v1.2.3


From 67a33eed40f0a551fdf9bf1059928cda1c2d7fdb Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Wed, 18 Jun 2008 10:15:21 -0700
Subject: AtomicSimpleCPU: Separate data stalls from instruction stalls.
 Separate simulation of icache stalls and dat stalls.

---
 src/cpu/simple/AtomicSimpleCPU.py |  3 ++-
 src/cpu/simple/atomic.cc          | 39 +++++++++++++++++++++++++--------------
 src/cpu/simple/atomic.hh          |  6 ++++--
 3 files changed, 31 insertions(+), 17 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 28c2aa9c9..a0b358439 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -33,7 +33,8 @@ from BaseCPU import BaseCPU
 class AtomicSimpleCPU(BaseCPU):
     type = 'AtomicSimpleCPU'
     width = Param.Int(1, "CPU width")
-    simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
+    simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
+    simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
     if build_env['FULL_SYSTEM']:
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index acd280568..b25d3330f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -153,8 +153,9 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 }
 
 AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
-    : BaseSimpleCPU(p), tickEvent(this),
-      width(p->width), simulate_stalls(p->simulate_stalls),
+    : BaseSimpleCPU(p), tickEvent(this), width(p->width),
+      simulate_data_stalls(p->simulate_data_stalls),
+      simulate_inst_stalls(p->simulate_inst_stalls),
       icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
       physmemPort(name() + "-iport", this), hasPhysMemPort(false)
 {
@@ -711,7 +712,7 @@ AtomicSimpleCPU::tick()
 {
     DPRINTF(SimpleCPU, "Tick\n");
 
-    Tick latency = ticks(1); // instruction takes one cycle by default
+    Tick latency = 0;
 
     for (int i = 0; i < width; ++i) {
         numCycles++;
@@ -769,16 +770,21 @@ AtomicSimpleCPU::tick()
                         curStaticInst->isFirstMicroop()))
                 instCnt++;
 
-            if (simulate_stalls) {
-                Tick icache_stall =
-                    icache_access ? icache_latency - ticks(1) : 0;
-                Tick dcache_stall =
-                    dcache_access ? dcache_latency - ticks(1) : 0;
-                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
-                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
-                    latency += ticks(stall_cycles+1);
-                else
-                    latency += ticks(stall_cycles);
+            Tick stall_ticks = 0;
+            if (simulate_inst_stalls && icache_access)
+                stall_ticks += icache_latency;
+
+            if (simulate_data_stalls && dcache_access)
+                stall_ticks += dcache_latency;
+
+            if (stall_ticks) {
+                Tick stall_cycles = stall_ticks / ticks(1);
+                Tick aligned_stall_ticks = ticks(stall_cycles);
+
+                if (aligned_stall_ticks < stall_ticks)
+                    aligned_stall_ticks += 1;
+
+                latency += aligned_stall_ticks;
             }
 
         }
@@ -786,6 +792,10 @@ AtomicSimpleCPU::tick()
             advancePC(fault);
     }
 
+    // instruction takes at least one cycle
+    if (latency < ticks(1))
+        latency = ticks(1);
+
     if (_status != Idle)
         tickEvent.schedule(curTick + latency);
 }
@@ -819,7 +829,8 @@ AtomicSimpleCPUParams::create()
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
     params->width = width;
-    params->simulate_stalls = simulate_stalls;
+    params->simulate_data_stalls = simulate_data_stalls;
+    params->simulate_inst_stalls = simulate_inst_stalls;
     params->system = system;
     params->cpu_id = cpu_id;
     params->tracer = tracer;
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 19bc0e13b..ccea15073 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -39,7 +39,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     struct Params : public BaseSimpleCPU::Params {
         int width;
-        bool simulate_stalls;
+        bool simulate_data_stalls;
+        bool simulate_inst_stalls;
     };
 
     AtomicSimpleCPU(Params *params);
@@ -74,7 +75,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     TickEvent tickEvent;
 
     const int width;
-    const bool simulate_stalls;
+    const bool simulate_data_stalls;
+    const bool simulate_inst_stalls;
 
     // main simulation loop (one cycle)
     void tick();
-- 
cgit v1.2.3


From 9bd0bfe559d8c9633c5686ccf100ab921eb6eda2 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 1 Jul 2008 10:24:09 -0400
Subject: After a checkpoint (and thus a stats reset), the
 not_idle_fraction/notIdleFraction statistic is really wrong. The
 notIdleFraction statistic isn't updated when the statistics reset, probably
 because the cpu Status information was pulled into the atomic and timing
 cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
 care to comment on the odd naming of the Status instance? It shouldn't just
 be status because that is confusing with Port::Status, but _status seems a
 bit strage too.

---
 src/cpu/simple/atomic.cc |  5 +----
 src/cpu/simple/atomic.hh | 13 -------------
 src/cpu/simple/base.cc   |  4 +++-
 src/cpu/simple/base.hh   | 14 ++++++++++++++
 src/cpu/simple/timing.cc |  4 ++--
 src/cpu/simple/timing.hh | 18 ------------------
 6 files changed, 20 insertions(+), 38 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b25d3330f..6b07502ef 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -176,8 +176,6 @@ AtomicSimpleCPU::serialize(ostream &os)
 {
     SimObject::State so_state = SimObject::getState();
     SERIALIZE_ENUM(so_state);
-    Status _status = status();
-    SERIALIZE_ENUM(_status);
     BaseSimpleCPU::serialize(os);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
@@ -188,7 +186,6 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
     SimObject::State so_state;
     UNSERIALIZE_ENUM(so_state);
-    UNSERIALIZE_ENUM(_status);
     BaseSimpleCPU::unserialize(cp, section);
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 }
@@ -213,7 +210,7 @@ AtomicSimpleCPU::resume()
 void
 AtomicSimpleCPU::switchOut()
 {
-    assert(status() == Running || status() == Idle);
+    assert(_status == Running || _status == Idle);
     _status = SwitchedOut;
 
     tickEvent.squash();
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index ccea15073..008397533 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -48,19 +48,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     virtual void init();
 
-  public:
-    //
-    enum Status {
-        Running,
-        Idle,
-        SwitchedOut
-    };
-
-  protected:
-    Status _status;
-
-    Status status() const { return _status; }
-
   private:
 
     struct TickEvent : public Event
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4a91a9e12..0c1162032 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -174,12 +174,13 @@ void
 BaseSimpleCPU::resetStats()
 {
 //    startNumInst = numInst;
-    // notIdleFraction = (_status != Idle);
+     notIdleFraction = (_status != Idle);
 }
 
 void
 BaseSimpleCPU::serialize(ostream &os)
 {
+    SERIALIZE_ENUM(_status);
     BaseCPU::serialize(os);
 //    SERIALIZE_SCALAR(inst);
     nameOut(os, csprintf("%s.xc.0", name()));
@@ -189,6 +190,7 @@ BaseSimpleCPU::serialize(ostream &os)
 void
 BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
+    UNSERIALIZE_ENUM(_status);
     BaseCPU::unserialize(cp, section);
 //    UNSERIALIZE_SCALAR(inst);
     thread->unserialize(cp, csprintf("%s.xc.0", section));
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 918965fdb..62bb31de8 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -129,6 +129,20 @@ class BaseSimpleCPU : public BaseCPU
   protected:
     int cpuId;
 
+    enum Status {
+        Idle,
+        Running,
+        IcacheRetry,
+        IcacheWaitResponse,
+        IcacheWaitSwitch,
+        DcacheRetry,
+        DcacheWaitResponse,
+        DcacheWaitSwitch,
+        SwitchedOut
+    };
+
+    Status _status;
+
   public:
 
 #if FULL_SYSTEM
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d0c7dd787..2cf7d584d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -145,7 +145,7 @@ TimingSimpleCPU::drain(Event *drain_event)
 {
     // TimingSimpleCPU is ready to drain if it's not waiting for
     // an access to complete.
-    if (status() == Idle || status() == Running || status() == SwitchedOut) {
+    if (_status == Idle || _status == Running || _status == SwitchedOut) {
         changeState(SimObject::Drained);
         return 0;
     } else {
@@ -179,7 +179,7 @@ TimingSimpleCPU::resume()
 void
 TimingSimpleCPU::switchOut()
 {
-    assert(status() == Running || status() == Idle);
+    assert(_status == Running || _status == Idle);
     _status = SwitchedOut;
     numCycles += tickToCycles(curTick - previousTick);
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index f8b77604a..a748d47b4 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -46,24 +46,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void init();
 
   public:
-    //
-    enum Status {
-        Idle,
-        Running,
-        IcacheRetry,
-        IcacheWaitResponse,
-        IcacheWaitSwitch,
-        DcacheRetry,
-        DcacheWaitResponse,
-        DcacheWaitSwitch,
-        SwitchedOut
-    };
-
-  protected:
-    Status _status;
-
-    Status status() const { return _status; }
-
     Event *drainEvent;
 
   private:
-- 
cgit v1.2.3


From 50e3e50e1ac592b357a47eecdc3c99a528172870 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 1 Jul 2008 10:24:16 -0400
Subject: Make the cached virtPort have a thread context so it can do
 everything that a newly created one can.

---
 src/cpu/simple/atomic.cc | 2 +-
 src/cpu/simple/timing.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 6b07502ef..0e04a36b2 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -148,7 +148,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 #if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
-    cpu->tcBase()->connectMemPorts();
+    cpu->tcBase()->connectMemPorts(cpu->tcBase());
 #endif
 }
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2cf7d584d..b86d4b2d7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -766,7 +766,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
 #if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
-    cpu->tcBase()->connectMemPorts();
+    cpu->tcBase()->connectMemPorts(cpu->tcBase());
 #endif
 }
 
-- 
cgit v1.2.3


From 8e7ddce28493c93564aeb20f1856fbe6bff0ece4 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@gmail.com>
Date: Tue, 15 Jul 2008 14:38:51 -0400
Subject: Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.

---
 src/cpu/simple/timing.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index b86d4b2d7..4451dfe81 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -730,7 +730,9 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
         traceData = NULL;
     }
 
-    if (pkt->isRead() && pkt->isLocked()) {
+    // the locked flag may be cleared on the response packet, so check
+    // pkt->req and not pkt to see if it was a load-locked
+    if (pkt->isRead() && pkt->req->isLocked()) {
         TheISA::handleLockedRead(thread, pkt->req);
     }
 
-- 
cgit v1.2.3


From ee62a0fec8e63f45f816c61ab9fb28aba7414185 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Mon, 11 Aug 2008 12:22:16 -0700
Subject: params: Convert the CPU objects to use the auto generated param
 structs. A whole bunch of stuff has been converted to use the new params
 stuff, but the CPU wasn't one of them.  While we're at it, make some things a
 bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up
 a bit more at the end.

---
 src/cpu/simple/AtomicSimpleCPU.py |  6 +++---
 src/cpu/simple/BaseSimpleCPU.py   | 34 ++++++++++++++++++++++++++++++++++
 src/cpu/simple/SConscript         |  1 +
 src/cpu/simple/TimingSimpleCPU.py |  6 +++---
 src/cpu/simple/atomic.cc          | 37 ++++---------------------------------
 src/cpu/simple/atomic.hh          |  9 ++-------
 src/cpu/simple/base.cc            |  6 ++++--
 src/cpu/simple/base.hh            | 12 +++---------
 src/cpu/simple/timing.cc          | 34 ++++------------------------------
 src/cpu/simple/timing.hh          |  7 +++----
 10 files changed, 61 insertions(+), 91 deletions(-)
 create mode 100644 src/cpu/simple/BaseSimpleCPU.py

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index a0b358439..e1c1e4cd1 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -28,9 +28,9 @@
 
 from m5.params import *
 from m5 import build_env
-from BaseCPU import BaseCPU
+from BaseSimpleCPU import BaseSimpleCPU
 
-class AtomicSimpleCPU(BaseCPU):
+class AtomicSimpleCPU(BaseSimpleCPU):
     type = 'AtomicSimpleCPU'
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
@@ -42,5 +42,5 @@ class AtomicSimpleCPU(BaseCPU):
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
-    _mem_ports = BaseCPU._mem_ports + \
+    _mem_ports = BaseSimpleCPU._mem_ports + \
                     ['icache_port', 'dcache_port', 'physmem_port']
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
new file mode 100644
index 000000000..9f528bc20
--- /dev/null
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2008 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from BaseCPU import BaseCPU
+
+class BaseSimpleCPU(BaseCPU):
+    type = 'BaseSimpleCPU'
+    abstract = True
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index c090a938c..76598666f 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -47,3 +47,4 @@ if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
 
 if need_simple_base:
     Source('base.cc')
+    SimObject('BaseSimpleCPU.py')
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 7e777e813..f2b14a175 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -28,9 +28,9 @@
 
 from m5.params import *
 from m5 import build_env
-from BaseCPU import BaseCPU
+from BaseSimpleCPU import BaseSimpleCPU
 
-class TimingSimpleCPU(BaseCPU):
+class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
@@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU):
         profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
+    _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0e04a36b2..7ed1ee0c3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -152,7 +152,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 #endif
 }
 
-AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
+AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
     : BaseSimpleCPU(p), tickEvent(this), width(p->width),
       simulate_data_stalls(p->simulate_data_stalls),
       simulate_inst_stalls(p->simulate_inst_stalls),
@@ -812,39 +812,10 @@ AtomicSimpleCPU::printAddr(Addr a)
 AtomicSimpleCPU *
 AtomicSimpleCPUParams::create()
 {
-    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
-    params->name = name;
-    params->numberOfThreads = 1;
-    params->max_insts_any_thread = max_insts_any_thread;
-    params->max_insts_all_threads = max_insts_all_threads;
-    params->max_loads_any_thread = max_loads_any_thread;
-    params->max_loads_all_threads = max_loads_all_threads;
-    params->progress_interval = progress_interval;
-    params->deferRegistration = defer_registration;
-    params->phase = phase;
-    params->clock = clock;
-    params->functionTrace = function_trace;
-    params->functionTraceStart = function_trace_start;
-    params->width = width;
-    params->simulate_data_stalls = simulate_data_stalls;
-    params->simulate_inst_stalls = simulate_inst_stalls;
-    params->system = system;
-    params->cpu_id = cpu_id;
-    params->tracer = tracer;
-
-    params->itb = itb;
-    params->dtb = dtb;
-#if FULL_SYSTEM
-    params->profile = profile;
-    params->do_quiesce = do_quiesce;
-    params->do_checkpoint_insts = do_checkpoint_insts;
-    params->do_statistics_insts = do_statistics_insts;
-#else
+    numThreads = 1;
+#if !FULL_SYSTEM
     if (workload.size() != 1)
         panic("only one workload allowed");
-    params->process = workload[0];
 #endif
-
-    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
-    return cpu;
+    return new AtomicSimpleCPU(this);
 }
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 008397533..24400df22 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -32,18 +32,13 @@
 #define __CPU_SIMPLE_ATOMIC_HH__
 
 #include "cpu/simple/base.hh"
+#include "params/AtomicSimpleCPU.hh"
 
 class AtomicSimpleCPU : public BaseSimpleCPU
 {
   public:
 
-    struct Params : public BaseSimpleCPU::Params {
-        int width;
-        bool simulate_data_stalls;
-        bool simulate_inst_stalls;
-    };
-
-    AtomicSimpleCPU(Params *params);
+    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
     virtual ~AtomicSimpleCPU();
 
     virtual void init();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0c1162032..3fd699868 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -65,16 +65,18 @@
 #include "mem/mem_object.hh"
 #endif // FULL_SYSTEM
 
+#include "params/BaseSimpleCPU.hh"
+
 using namespace std;
 using namespace TheISA;
 
-BaseSimpleCPU::BaseSimpleCPU(Params *p)
+BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
     : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
 {
 #if FULL_SYSTEM
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
 #else
-    thread = new SimpleThread(this, /* thread_num */ 0, p->process,
+    thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
             p->itb, p->dtb, /* asid */ 0);
 #endif // !FULL_SYSTEM
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 62bb31de8..aeae1a3d8 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -76,6 +76,8 @@ namespace Trace {
     class InstRecord;
 }
 
+class BaseSimpleCPUParams;
+
 
 class BaseSimpleCPU : public BaseCPU
 {
@@ -107,15 +109,7 @@ class BaseSimpleCPU : public BaseCPU
     };
 
   public:
-    struct Params : public BaseCPU::Params
-    {
-        TheISA::ITB *itb;
-        TheISA::DTB *dtb;
-#if !FULL_SYSTEM
-        Process *process;
-#endif
-    };
-    BaseSimpleCPU(Params *params);
+    BaseSimpleCPU(BaseSimpleCPUParams *params);
     virtual ~BaseSimpleCPU();
 
   public:
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4451dfe81..ac67341ff 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -104,7 +104,7 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
     Event::schedule(t);
 }
 
-TimingSimpleCPU::TimingSimpleCPU(Params *p)
+TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
     : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
 {
     _status = Idle;
@@ -852,36 +852,10 @@ TimingSimpleCPU::printAddr(Addr a)
 TimingSimpleCPU *
 TimingSimpleCPUParams::create()
 {
-    TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
-    params->name = name;
-    params->numberOfThreads = 1;
-    params->max_insts_any_thread = max_insts_any_thread;
-    params->max_insts_all_threads = max_insts_all_threads;
-    params->max_loads_any_thread = max_loads_any_thread;
-    params->max_loads_all_threads = max_loads_all_threads;
-    params->progress_interval = progress_interval;
-    params->deferRegistration = defer_registration;
-    params->clock = clock;
-    params->phase = phase;
-    params->functionTrace = function_trace;
-    params->functionTraceStart = function_trace_start;
-    params->system = system;
-    params->cpu_id = cpu_id;
-    params->tracer = tracer;
-
-    params->itb = itb;
-    params->dtb = dtb;
-#if FULL_SYSTEM
-    params->profile = profile;
-    params->do_quiesce = do_quiesce;
-    params->do_checkpoint_insts = do_checkpoint_insts;
-    params->do_statistics_insts = do_statistics_insts;
-#else
+    numThreads = 1;
+#if !FULL_SYSTEM
     if (workload.size() != 1)
         panic("only one workload allowed");
-    params->process = workload[0];
 #endif
-
-    TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
-    return cpu;
+    return new TimingSimpleCPU(this);
 }
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index a748d47b4..e405f6a41 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -33,14 +33,13 @@
 
 #include "cpu/simple/base.hh"
 
+#include "params/TimingSimpleCPU.hh"
+
 class TimingSimpleCPU : public BaseSimpleCPU
 {
   public:
 
-    struct Params : public BaseSimpleCPU::Params {
-    };
-
-    TimingSimpleCPU(Params *params);
+    TimingSimpleCPU(TimingSimpleCPUParams * params);
     virtual ~TimingSimpleCPU();
 
     virtual void init();
-- 
cgit v1.2.3


From 8d018aef0f9de7129a77172a4164f36b2b093be6 Mon Sep 17 00:00:00 2001
From: Richard Strong <rstrong@hp.com>
Date: Mon, 18 Aug 2008 10:50:58 -0700
Subject: Changed BaseCPU::ProfileEvent's interval member to be of type Tick.
 This was done to be consistent with its python type of a latency.  In
 addition, the multiple definitions of profile in the different cpu models
 caused problems for intialization of the interval value. If a child class's
 profile value was defined, the parent BaseCPU::ProfileEvent interval field
 would be initialized with a garbage value. The fix was to remove the multiple
 redifitions of profile in the child CPU classes.

---
 src/cpu/simple/AtomicSimpleCPU.py | 2 --
 src/cpu/simple/TimingSimpleCPU.py | 2 --
 2 files changed, 4 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index e1c1e4cd1..87e8b5509 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -37,8 +37,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index f2b14a175..b7f044bfa 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -34,8 +34,6 @@ class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
-    if build_env['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
-- 
cgit v1.2.3


From 3633a916c299a1f5df9f6d34a0215cdae68a3e93 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 19 Aug 2008 21:59:09 -0700
Subject: CPU: Get rid of two more duplicated CPU params.

---
 src/cpu/simple/AtomicSimpleCPU.py | 2 --
 src/cpu/simple/TimingSimpleCPU.py | 2 --
 2 files changed, 4 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 87e8b5509..b7174bb43 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -35,8 +35,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     physmem_port = Port("Physical Memory Port")
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index b7f044bfa..ce6839241 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -32,8 +32,6 @@ from BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
-    function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
-- 
cgit v1.2.3


From 3a3e356f4e61e86f6f1427dd85cf1e41fa9125c0 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 10 Sep 2008 14:26:15 -0400
Subject: style: Remove non-leading tabs everywhere they shouldn't be.
 Developers should configure their editors to not insert tabs

---
 src/cpu/simple/base.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index aeae1a3d8..b7fcf1708 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -227,7 +227,7 @@ class BaseSimpleCPU : public BaseCPU
     // These functions are only used in CPU models that split
     // effective address computation from the actual memory access.
     void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
-    Addr getEA() 	{ panic("BaseSimpleCPU::getEA() not implemented\n");
+    Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
         M5_DUMMY_RETURN}
 
     void prefetch(Addr addr, unsigned flags)
-- 
cgit v1.2.3


From e06321091d4e931ff1a4d753e56d76f9746c3cd2 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Thu, 9 Oct 2008 04:58:24 -0700
Subject: eventq: convert all usage of events to use the new API. For now,
 there is still a single global event queue, but this is necessary for making
 the steps towards a parallelized m5.

---
 src/cpu/simple/atomic.cc | 15 +++++++--------
 src/cpu/simple/timing.cc | 16 +++++++++-------
 src/cpu/simple/timing.hh |  3 +--
 3 files changed, 17 insertions(+), 17 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 7ed1ee0c3..154a66162 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -43,7 +43,7 @@ using namespace std;
 using namespace TheISA;
 
 AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
-    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
+    : Event(CPU_Tick_Pri), cpu(c)
 {
 }
 
@@ -201,9 +201,8 @@ AtomicSimpleCPU::resume()
 
     changeState(SimObject::Running);
     if (thread->status() == ThreadContext::Active) {
-        if (!tickEvent.scheduled()) {
-            tickEvent.schedule(nextCycle());
-        }
+        if (!tickEvent.scheduled())
+            schedule(tickEvent, nextCycle());
     }
 }
 
@@ -230,7 +229,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         ThreadContext *tc = threadContexts[i];
         if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
-            tickEvent.schedule(nextCycle());
+            schedule(tickEvent, nextCycle());
             break;
         }
     }
@@ -260,7 +259,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
     numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
 
     //Make sure ticks are still on multiples of cycles
-    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
+    schedule(tickEvent, nextCycle(curTick + ticks(delay)));
     _status = Running;
 }
 
@@ -278,7 +277,7 @@ AtomicSimpleCPU::suspendContext(int thread_num)
     // tick event may not be scheduled if this gets called from inside
     // an instruction's execution, e.g. "quiesce"
     if (tickEvent.scheduled())
-        tickEvent.deschedule();
+        deschedule(tickEvent);
 
     notIdleFraction--;
     _status = Idle;
@@ -794,7 +793,7 @@ AtomicSimpleCPU::tick()
         latency = ticks(1);
 
     if (_status != Idle)
-        tickEvent.schedule(curTick + latency);
+        schedule(tickEvent, curTick + latency);
 }
 
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ac67341ff..c4635d6a3 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -101,7 +101,7 @@ void
 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 {
     pkt = _pkt;
-    Event::schedule(t);
+    cpu->schedule(this, t);
 }
 
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
@@ -165,7 +165,7 @@ TimingSimpleCPU::resume()
         // Delete the old event if it existed.
         if (fetchEvent) {
             if (fetchEvent->scheduled())
-                fetchEvent->deschedule();
+                deschedule(fetchEvent);
 
             delete fetchEvent;
         }
@@ -186,7 +186,7 @@ TimingSimpleCPU::switchOut()
     // If we've been scheduled to resume but are then told to switch out,
     // we'll need to cancel it.
     if (fetchEvent && fetchEvent->scheduled())
-        fetchEvent->deschedule();
+        deschedule(fetchEvent);
 }
 
 
@@ -228,7 +228,8 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
+    fetchEvent = new FetchEvent(this);
+    schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
 }
 
 
@@ -819,10 +820,11 @@ TimingSimpleCPU::DcachePort::recvRetry()
     }
 }
 
-TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
-    : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
+TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
+    Tick t)
+    : pkt(_pkt), cpu(_cpu)
 {
-    schedule(t);
+    cpu->schedule(this, t);
 }
 
 void
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index e405f6a41..081051ea7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -80,8 +80,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
             PacketPtr pkt;
             TimingSimpleCPU *cpu;
 
-            TickEvent(TimingSimpleCPU *_cpu)
-                :Event(&mainEventQueue), cpu(_cpu) {}
+            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
             const char *description() const { return "Timing CPU tick"; }
             void schedule(PacketPtr _pkt, Tick t);
         };
-- 
cgit v1.2.3


From da7209ec93f3cdad11c02906357f06fa29652996 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 11 Oct 2008 02:27:21 -0700
Subject: CPU: Eliminate the hwrei function.

---
 src/cpu/simple/base.hh | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b7fcf1708..b28a690bb 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -413,7 +413,6 @@ class BaseSimpleCPU : public BaseCPU
     //Fault CacheOp(uint8_t Op, Addr EA);
 
 #if FULL_SYSTEM
-    Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else
-- 
cgit v1.2.3


From f621b7b81f0913612381d5dc4993f52bb2116902 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 11 Oct 2008 12:17:24 -0700
Subject: CPU: Eliminate the simPalCheck funciton.

---
 src/cpu/simple/base.hh | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b28a690bb..03c20a6f2 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -414,7 +414,6 @@ class BaseSimpleCPU : public BaseCPU
 
 #if FULL_SYSTEM
     void ev5_trap(Fault fault) { fault->invoke(tc); }
-    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else
     void syscall(int64_t callnum) { thread->syscall(callnum); }
 #endif
-- 
cgit v1.2.3


From d9f9c967fbe651e09d444e460a9b1c5a450b1cd2 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 09:09:56 -0700
Subject: Turn Interrupts objects into SimObjects. Also, move local APIC state
 into x86's Interrupts object.

---
 src/cpu/simple/base.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 3fd699868..48e5db347 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -319,10 +319,10 @@ BaseSimpleCPU::checkForInterrupts()
 {
 #if FULL_SYSTEM
     if (check_interrupts(tc)) {
-        Fault interrupt = interrupts.getInterrupt(tc);
+        Fault interrupt = interrupts->getInterrupt(tc);
 
         if (interrupt != NoFault) {
-            interrupts.updateIntrInfo(tc);
+            interrupts->updateIntrInfo(tc);
             interrupt->invoke(tc);
         }
     }
-- 
cgit v1.2.3


From c9ea0b73492bf116c836c54199898f29d9664bc0 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 16:59:55 -0700
Subject: CPU: Make the highest order bit in the micro pc determine if it's
 combinational or from the ROM.

---
 src/cpu/simple/base.cc | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 48e5db347..d207bda14 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -368,9 +368,13 @@ BaseSimpleCPU::preExecute()
     // decode the instruction
     inst = gtoh(inst);
 
-    //If we're not in the middle of a macro instruction
-    if (!curMacroStaticInst) {
+    MicroPC upc = thread->readMicroPC();
 
+    if (isRomMicroPC(upc)) {
+        stayAtPC = false;
+        curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
+    } else if (!curMacroStaticInst) {
+        //We're not in the middle of a macro instruction
         StaticInstPtr instPtr = NULL;
 
         //Predecode, ie bundle up an ExtMachInst
@@ -401,15 +405,13 @@ BaseSimpleCPU::preExecute()
         //out micro ops
         if (instPtr && instPtr->isMacroop()) {
             curMacroStaticInst = instPtr;
-            curStaticInst = curMacroStaticInst->
-                fetchMicroop(thread->readMicroPC());
+            curStaticInst = curMacroStaticInst->fetchMicroop(upc);
         } else {
             curStaticInst = instPtr;
         }
     } else {
         //Read the next micro op from the macro op
-        curStaticInst = curMacroStaticInst->
-            fetchMicroop(thread->readMicroPC());
+        curStaticInst = curMacroStaticInst->fetchMicroop(upc);
     }
 
     //If we decoded an instruction this "tick", record information about it.
@@ -469,22 +471,23 @@ BaseSimpleCPU::advancePC(Fault fault)
     if (fault != NoFault) {
         curMacroStaticInst = StaticInst::nullStaticInstPtr;
         predecoder.reset();
-        thread->setMicroPC(0);
-        thread->setNextMicroPC(1);
+        thread->setMicroPC(normalMicroPC(0));
+        thread->setNextMicroPC(normalMicroPC(1));
         fault->invoke(tc);
     } else {
         //If we're at the last micro op for this instruction
         if (curStaticInst && curStaticInst->isLastMicroop()) {
-            //We should be working with a macro op
-            assert(curMacroStaticInst);
+            //We should be working with a macro op or be in the ROM
+            assert(curMacroStaticInst ||
+                    isRomMicroPC(thread->readMicroPC()));
             //Close out this macro op, and clean up the
             //microcode state
             curMacroStaticInst = StaticInst::nullStaticInstPtr;
-            thread->setMicroPC(0);
-            thread->setNextMicroPC(1);
+            thread->setMicroPC(normalMicroPC(0));
+            thread->setNextMicroPC(normalMicroPC(1));
         }
         //If we're still in a macro op
-        if (curMacroStaticInst) {
+        if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
             //Advance the micro pc
             thread->setMicroPC(thread->readNextMicroPC());
             //Advance the "next" micro pc. Note that there are no delay
-- 
cgit v1.2.3


From 0756dbb37a432b895b019e49862fcd7f42e1bd00 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 19:32:06 -0700
Subject: X86: Don't fetch in the simple CPU if you're in the ROM.

---
 src/cpu/simple/atomic.cc | 40 +++++++++++++++++++---------------
 src/cpu/simple/timing.cc | 56 +++++++++++++++++++++++++++++-------------------
 2 files changed, 57 insertions(+), 39 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 154a66162..878f69f0c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -718,31 +718,37 @@ AtomicSimpleCPU::tick()
 
         checkPcEventQueue();
 
-        Fault fault = setupFetchRequest(&ifetch_req);
+        Fault fault = NoFault;
+
+        bool fromRom = isRomMicroPC(thread->readMicroPC());
+        if (!fromRom)
+            fault = setupFetchRequest(&ifetch_req);
 
         if (fault == NoFault) {
             Tick icache_latency = 0;
             bool icache_access = false;
             dcache_access = false; // assume no dcache access
 
-            //Fetch more instruction memory if necessary
-            //if(predecoder.needMoreBytes())
-            //{
-                icache_access = true;
-                Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
-                                           Packet::Broadcast);
-                ifetch_pkt.dataStatic(&inst);
-
-                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
-                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
-                else
-                    icache_latency = icachePort.sendAtomic(&ifetch_pkt);
+            if (!fromRom) {
+                //Fetch more instruction memory if necessary
+                //if(predecoder.needMoreBytes())
+                //{
+                    icache_access = true;
+                    Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
+                                               Packet::Broadcast);
+                    ifetch_pkt.dataStatic(&inst);
+
+                    if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
+                        icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
+                    else
+                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
 
-                assert(!ifetch_pkt.isError());
+                    assert(!ifetch_pkt.isError());
 
-                // ifetch_req is initialized to read the instruction directly
-                // into the CPU object's inst field.
-            //}
+                    // ifetch_req is initialized to read the instruction directly
+                    // into the CPU object's inst field.
+                //}
+            }
 
             preExecute();
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c4635d6a3..0cda9a0a3 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -531,28 +531,35 @@ TimingSimpleCPU::fetch()
 
     checkPcEventQueue();
 
-    Request *ifetch_req = new Request();
-    ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
-    Fault fault = setupFetchRequest(ifetch_req);
+    bool fromRom = isRomMicroPC(thread->readMicroPC());
 
-    ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
-    ifetch_pkt->dataStatic(&inst);
+    if (!fromRom) {
+        Request *ifetch_req = new Request();
+        ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
+        Fault fault = setupFetchRequest(ifetch_req);
 
-    if (fault == NoFault) {
-        if (!icachePort.sendTiming(ifetch_pkt)) {
-            // Need to wait for retry
-            _status = IcacheRetry;
+        ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
+        ifetch_pkt->dataStatic(&inst);
+
+        if (fault == NoFault) {
+            if (!icachePort.sendTiming(ifetch_pkt)) {
+                // Need to wait for retry
+                _status = IcacheRetry;
+            } else {
+                // Need to wait for cache to respond
+                _status = IcacheWaitResponse;
+                // ownership of packet transferred to memory system
+                ifetch_pkt = NULL;
+            }
         } else {
-            // Need to wait for cache to respond
-            _status = IcacheWaitResponse;
-            // ownership of packet transferred to memory system
-            ifetch_pkt = NULL;
+            delete ifetch_req;
+            delete ifetch_pkt;
+            // fetch fault: advance directly to next instruction (fault handler)
+            advanceInst(fault);
         }
     } else {
-        delete ifetch_req;
-        delete ifetch_pkt;
-        // fetch fault: advance directly to next instruction (fault handler)
-        advanceInst(fault);
+        _status = IcacheWaitResponse;
+        completeIfetch(NULL);
     }
 
     numCycles += tickToCycles(curTick - previousTick);
@@ -581,7 +588,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 
     // received a response from the icache: execute the received
     // instruction
-    assert(!pkt->isError());
+
+    assert(!pkt || !pkt->isError());
     assert(_status == IcacheWaitResponse);
 
     _status = Running;
@@ -590,8 +598,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
     previousTick = curTick;
 
     if (getState() == SimObject::Draining) {
-        delete pkt->req;
-        delete pkt;
+        if (pkt) {
+            delete pkt->req;
+            delete pkt;
+        }
 
         completeDrain();
         return;
@@ -658,8 +668,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         advanceInst(fault);
     }
 
-    delete pkt->req;
-    delete pkt;
+    if (pkt) {
+        delete pkt->req;
+        delete pkt;
+    }
 }
 
 void
-- 
cgit v1.2.3


From 809f6cb6d1c199563664305fe3b0b286c54dbea7 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 12 Oct 2008 23:52:02 -0700
Subject: CPU: Explain why some code is commented out.

---
 src/cpu/simple/atomic.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 878f69f0c..30f4a5c5e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -730,6 +730,10 @@ AtomicSimpleCPU::tick()
             dcache_access = false; // assume no dcache access
 
             if (!fromRom) {
+                // This is commented out because the predecoder would act like
+                // a tiny cache otherwise. It wouldn't be flushed when needed
+                // like the I cache. It should be flushed, and when that works
+                // this code should be uncommented.
                 //Fetch more instruction memory if necessary
                 //if(predecoder.needMoreBytes())
                 //{
-- 
cgit v1.2.3


From b760b99f4d9f5469d88c67ae8a06e5f9543a43e7 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Mon, 20 Oct 2008 16:22:59 -0400
Subject: O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3
 CPU.  Removing hwrei causes the instruction after the hwrei to be fetched
 before the ITB/DTB_CM register is updated in a call pal call sys and thus the
 translation fails because the user is attempting to access a super page
 address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
---
 src/cpu/simple/base.hh | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 03c20a6f2..b7fcf1708 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -413,7 +413,9 @@ class BaseSimpleCPU : public BaseCPU
     //Fault CacheOp(uint8_t Op, Addr EA);
 
 #if FULL_SYSTEM
+    Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
+    bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 #else
     void syscall(int64_t callnum) { thread->syscall(callnum); }
 #endif
-- 
cgit v1.2.3


From 9836d81c2bba97e36c43ca22feee1d51a12ce6ac Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Tue, 21 Oct 2008 07:12:53 -0700
Subject: style: Use the correct m5 style for things relating to interrupts.

---
 src/cpu/simple/base.cc | 6 +++---
 src/cpu/simple/base.hh | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d207bda14..b3379cddb 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -303,9 +303,9 @@ BaseSimpleCPU::dbg_vtophys(Addr addr)
 
 #if FULL_SYSTEM
 void
-BaseSimpleCPU::post_interrupt(int int_num, int index)
+BaseSimpleCPU::postInterrupt(int int_num, int index)
 {
-    BaseCPU::post_interrupt(int_num, index);
+    BaseCPU::postInterrupt(int_num, index);
 
     if (thread->status() == ThreadContext::Suspended) {
                 DPRINTF(Quiesce,"Suspended Processor awoke\n");
@@ -318,7 +318,7 @@ void
 BaseSimpleCPU::checkForInterrupts()
 {
 #if FULL_SYSTEM
-    if (check_interrupts(tc)) {
+    if (checkInterrupts(tc)) {
         Fault interrupt = interrupts->getInterrupt(tc);
 
         if (interrupt != NoFault) {
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b7fcf1708..dc736c22e 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -98,7 +98,7 @@ class BaseSimpleCPU : public BaseCPU
     }
 
   public:
-    void post_interrupt(int int_num, int index);
+    void postInterrupt(int int_num, int index);
 
     void zero_fill_64(Addr addr) {
       static int warned = 0;
-- 
cgit v1.2.3


From 95af120e601671e6819ca97b78a1879d4ab0d853 Mon Sep 17 00:00:00 2001
From: Clint Smullen <cws3k@cs.virginia.edu>
Date: Mon, 27 Oct 2008 18:18:04 -0400
Subject: CPU: The  API change to EventWrapper did not get propagated to the
 entirety of TimingSimpleCPU. The constructor no-longer schedules an event at
 construction and the implict conversion between int and bool was allowing the
 old code to compile without warning.

Signed-off By: Ali Saidi
---
 src/cpu/simple/timing.cc | 17 +++++------------
 src/cpu/simple/timing.hh |  2 +-
 2 files changed, 6 insertions(+), 13 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 0cda9a0a3..a6059f55f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -105,7 +105,7 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 }
 
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
-    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
+    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this)
 {
     _status = Idle;
 
@@ -114,7 +114,6 @@ TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
 
     ifetch_pkt = dcache_pkt = NULL;
     drainEvent = NULL;
-    fetchEvent = NULL;
     previousTick = 0;
     changeState(SimObject::Running);
 }
@@ -162,15 +161,10 @@ TimingSimpleCPU::resume()
     if (_status != SwitchedOut && _status != Idle) {
         assert(system->getMemoryMode() == Enums::timing);
 
-        // Delete the old event if it existed.
-        if (fetchEvent) {
-            if (fetchEvent->scheduled())
-                deschedule(fetchEvent);
+        if (fetchEvent.scheduled())
+           deschedule(fetchEvent);
 
-            delete fetchEvent;
-        }
-
-        fetchEvent = new FetchEvent(this, nextCycle());
+        schedule(fetchEvent, nextCycle());
     }
 
     changeState(SimObject::Running);
@@ -185,7 +179,7 @@ TimingSimpleCPU::switchOut()
 
     // If we've been scheduled to resume but are then told to switch out,
     // we'll need to cancel it.
-    if (fetchEvent && fetchEvent->scheduled())
+    if (fetchEvent.scheduled())
         deschedule(fetchEvent);
 }
 
@@ -228,7 +222,6 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent = new FetchEvent(this);
     schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
 }
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 081051ea7..0fc9b3152 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -192,7 +192,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
   private:
 
     typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
-    FetchEvent *fetchEvent;
+    FetchEvent fetchEvent;
 
     struct IprEvent : Event {
         Packet *pkt;
-- 
cgit v1.2.3


From c55a467a06eaa59c47c52a2adddc266b8e545589 Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Sun, 2 Nov 2008 21:56:57 -0500
Subject: make BaseCPU the provider of _cpuId, and cpuId() instead of being
 scattered across the subclasses. generally make it so that member data is
 _cpuId and accessor functions are cpuId(). The ID val comes from the python
 (default -1 if none provided), and if it is -1, the index of cpuList will be
 given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well
 as standard switch.

---
 src/cpu/simple/atomic.cc | 16 +++++++---------
 src/cpu/simple/base.hh   |  1 -
 src/cpu/simple/timing.cc | 15 +++++++--------
 3 files changed, 14 insertions(+), 18 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 30f4a5c5e..5e8ab9443 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -79,13 +79,12 @@ void
 AtomicSimpleCPU::init()
 {
     BaseCPU::init();
-    cpuId = tc->readCpuId();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, cpuId);
+        TheISA::initCPU(tc, _cpuId);
     }
 #endif
     if (hasPhysMemPort) {
@@ -94,9 +93,9 @@ AtomicSimpleCPU::init()
         physmemPort.getPeerAddressRanges(pmAddrList, snoop);
         physMemAddr = *pmAddrList.begin();
     }
-    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
-    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
-    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
+    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
+    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
+    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
 }
 
 bool
@@ -237,10 +236,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    cpuId = tc->readCpuId();
-    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
-    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
-    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
+    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
+    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
+    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
 }
 
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index dc736c22e..6e72b8f6c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -121,7 +121,6 @@ class BaseSimpleCPU : public BaseCPU
      */
     ThreadContext *tc;
   protected:
-    int cpuId;
 
     enum Status {
         Idle,
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a6059f55f..247899ca8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -57,13 +57,12 @@ void
 TimingSimpleCPU::init()
 {
     BaseCPU::init();
-    cpuId = tc->readCpuId();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, cpuId);
+        TheISA::initCPU(tc, _cpuId);
     }
 #endif
 }
@@ -203,7 +202,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    cpuId = tc->readCpuId();
+    _cpuId = tc->cpuId();
     previousTick = curTick;
 }
 
@@ -250,7 +249,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    cpuId, /* thread ID */ 0);
+                    _cpuId, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -301,7 +300,7 @@ TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
         int size, unsigned flags)
 {
     Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
 
     if (traceData) {
         traceData->setAddr(vaddr);
@@ -373,7 +372,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    cpuId, /* thread ID */ 0);
+                    _cpuId, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -442,7 +441,7 @@ TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
         int size, unsigned flags)
 {
     Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
 
     if (traceData) {
         traceData->setAddr(vaddr);
@@ -528,7 +527,7 @@ TimingSimpleCPU::fetch()
 
     if (!fromRom) {
         Request *ifetch_req = new Request();
-        ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
+        ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         Fault fault = setupFetchRequest(ifetch_req);
 
         ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
-- 
cgit v1.2.3


From d857faf073895dcfde97141bd6346fe5d4317f8e Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Sun, 2 Nov 2008 21:57:07 -0500
Subject: Add in Context IDs to the simulator.  From now on, cpuId is almost
 never used, the primary identifier for a hardware context should be
 contextId().  The concept of threads within a CPU remains, in the form of
 threadId() because sometimes you need to know which context within a cpu to
 manipulate.

---
 src/cpu/simple/atomic.cc | 3 ++-
 src/cpu/simple/timing.cc | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 5e8ab9443..feb8a7fc5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -84,7 +84,7 @@ AtomicSimpleCPU::init()
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, _cpuId);
+        TheISA::initCPU(tc, tc->contextId());
     }
 #endif
     if (hasPhysMemPort) {
@@ -93,6 +93,7 @@ AtomicSimpleCPU::init()
         physmemPort.getPeerAddressRanges(pmAddrList, snoop);
         physMemAddr = *pmAddrList.begin();
     }
+    // Atomic doesn't do MT right now, so contextId == threadId
     ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
     data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
     data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 247899ca8..ca1f0283e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -202,7 +202,6 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    _cpuId = tc->cpuId();
     previousTick = curTick;
 }
 
-- 
cgit v1.2.3


From 909380f3ee576f915f52c6245c59d41050a46f49 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 9 Nov 2008 21:55:01 -0800
Subject: X86: Make the timing simple CPU handle variable length instructions.

---
 src/cpu/simple/timing.cc | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ca1f0283e..f5eeeba60 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -561,7 +561,8 @@ TimingSimpleCPU::fetch()
 void
 TimingSimpleCPU::advanceInst(Fault fault)
 {
-    advancePC(fault);
+    if (fault != NoFault || !stayAtPC)
+        advancePC(fault);
 
     if (_status == Running) {
         // kick off fetch of next instruction... callback from icache
@@ -599,7 +600,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
     }
 
     preExecute();
-    if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
+    if (curStaticInst &&
+            curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
         // load or store: just send to dcache
         Fault fault = curStaticInst->initiateAcc(this, traceData);
         if (_status != Running) {
@@ -638,7 +640,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
                 instCnt++;
             advanceInst(fault);
         }
-    } else {
+    } else if (curStaticInst) {
         // non-memory instruction: execute completely now
         Fault fault = curStaticInst->execute(this, traceData);
 
@@ -657,6 +659,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
                     curStaticInst->isFirstMicroop()))
             instCnt++;
         advanceInst(fault);
+    } else {
+        advanceInst(NoFault);
     }
 
     if (pkt) {
-- 
cgit v1.2.3


From 846cb450f985eb249a5fc50e97f9e643cb1ebfc5 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 9 Nov 2008 21:56:28 -0800
Subject: CPU: Make unaligned accesses work in the timing simple CPU.

---
 src/cpu/simple/timing.cc | 366 +++++++++++++++++++++++++++++++++++++----------
 src/cpu/simple/timing.hh |  57 ++++++++
 2 files changed, 347 insertions(+), 76 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f5eeeba60..5d37fa620 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -241,57 +241,135 @@ TimingSimpleCPU::suspendContext(int thread_num)
     _status = Idle;
 }
 
+bool
+TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
+{
+    RequestPtr req = pkt->req;
+    if (req->isMmapedIpr()) {
+        Tick delay;
+        delay = TheISA::handleIprRead(thread->getTC(), pkt);
+        new IprEvent(pkt, this, nextCycle(curTick + delay));
+        _status = DcacheWaitResponse;
+        dcache_pkt = NULL;
+    } else if (!dcachePort.sendTiming(pkt)) {
+        _status = DcacheRetry;
+        dcache_pkt = pkt;
+    } else {
+        _status = DcacheWaitResponse;
+        // memory system takes ownership of packet
+        dcache_pkt = NULL;
+    }
+    return dcache_pkt == NULL;
+}
 
 template <class T>
 Fault
 TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
-    Request *req =
-        new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    _cpuId, /* thread ID */ 0);
-
-    if (traceData) {
-        traceData->setAddr(req->getVaddr());
-    }
+    Fault fault;
+    const int asid = 0;
+    const int thread_id = 0;
+    const Addr pc = thread->readPC();
+
+    PacketPtr pkt;
+    RequestPtr req;
+
+    int block_size = dcachePort.peerBlockSize();
+    int data_size = sizeof(T);
+
+    Addr second_addr = roundDown(addr + data_size - 1, block_size);
+
+    if (second_addr > addr) {
+        Addr first_size = second_addr - addr;
+        Addr second_size = data_size - first_size;
+        // Make sure we'll only need two accesses.
+        assert(roundDown(second_addr + second_size - 1, block_size) ==
+                second_addr);
+
+        /*
+         * Do the translations. If something isn't going to work, find out
+         * before we waste time setting up anything else.
+         */
+        req = new Request(asid, addr, first_size,
+                          flags, pc, _cpuId, thread_id);
+        fault = thread->translateDataReadReq(req);
+        if (fault != NoFault) {
+            delete req;
+            return fault;
+        }
+        Request *second_req =
+            new Request(asid, second_addr, second_size,
+                        flags, pc, _cpuId, thread_id);
+        fault = thread->translateDataReadReq(second_req);
+        if (fault != NoFault) {
+            delete req;
+            delete second_req;
+            return fault;
+        }
 
-   // translate to physical address
-    Fault fault = thread->translateDataReadReq(req);
+        T * data_ptr = new T;
+
+        /*
+         * This is the big packet that will hold the data we've gotten so far,
+         * if any, and also act as the response we actually give to the
+         * instruction.
+         */
+        Request *orig_req =
+            new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id);
+        orig_req->setPhys(req->getPaddr(), data_size, flags);
+        PacketPtr big_pkt =
+            new Packet(orig_req, MemCmd::ReadResp, Packet::Broadcast);
+        big_pkt->dataDynamic<T>(data_ptr);
+        SplitMainSenderState * main_send_state = new SplitMainSenderState;
+        big_pkt->senderState = main_send_state;
+        main_send_state->outstanding = 2;
+
+        // This is the packet we'll process now.
+        pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+        pkt->dataStatic<uint8_t>((uint8_t *)data_ptr);
+        pkt->senderState = new SplitFragmentSenderState(big_pkt, 0);
+
+        // This is the second half of the access we'll deal with later.
+        PacketPtr second_pkt =
+            new Packet(second_req, MemCmd::ReadReq, Packet::Broadcast);
+        second_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr + first_size);
+        second_pkt->senderState = new SplitFragmentSenderState(big_pkt, 1);
+        if (!handleReadPacket(pkt)) {
+            main_send_state->fragments[1] = second_pkt;
+        } else {
+            handleReadPacket(second_pkt);
+        }
+    } else {
+        req = new Request(asid, addr, data_size,
+                          flags, pc, _cpuId, thread_id);
 
-    // Now do the access.
-    if (fault == NoFault) {
-        PacketPtr pkt =
-            new Packet(req,
-                       (req->isLocked() ?
-                        MemCmd::LoadLockedReq : MemCmd::ReadReq),
-                       Packet::Broadcast);
-        pkt->dataDynamic<T>(new T);
+        // translate to physical address
+        Fault fault = thread->translateDataReadReq(req);
 
-        if (req->isMmapedIpr()) {
-            Tick delay;
-            delay = TheISA::handleIprRead(thread->getTC(), pkt);
-            new IprEvent(pkt, this, nextCycle(curTick + delay));
-            _status = DcacheWaitResponse;
-            dcache_pkt = NULL;
-        } else if (!dcachePort.sendTiming(pkt)) {
-            _status = DcacheRetry;
-            dcache_pkt = pkt;
-        } else {
-            _status = DcacheWaitResponse;
-            // memory system takes ownership of packet
-            dcache_pkt = NULL;
+        if (fault != NoFault) {
+            delete req;
+            return fault;
         }
 
-        // This will need a new way to tell if it has a dcache attached.
-        if (req->isUncacheable())
-            recordEvent("Uncached Read");
-    } else {
-        delete req;
+        pkt = new Packet(req,
+                         (req->isLocked() ?
+                          MemCmd::LoadLockedReq : MemCmd::ReadReq),
+                          Packet::Broadcast);
+        pkt->dataDynamic<T>(new T);
+
+        handleReadPacket(pkt);
     }
 
     if (traceData) {
         traceData->setData(data);
+        traceData->setAddr(addr);
     }
-    return fault;
+
+    // This will need a new way to tell if it has a dcache attached.
+    if (req->isUncacheable())
+        recordEvent("Uncached Read");
+
+    return NoFault;
 }
 
 Fault
@@ -364,26 +442,117 @@ TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
     return read(addr, (uint32_t&)data, flags);
 }
 
+bool
+TimingSimpleCPU::handleWritePacket()
+{
+    RequestPtr req = dcache_pkt->req;
+    if (req->isMmapedIpr()) {
+        Tick delay;
+        delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
+        new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
+        _status = DcacheWaitResponse;
+        dcache_pkt = NULL;
+    } else if (!dcachePort.sendTiming(dcache_pkt)) {
+        _status = DcacheRetry;
+    } else {
+        _status = DcacheWaitResponse;
+        // memory system takes ownership of packet
+        dcache_pkt = NULL;
+    }
+    return dcache_pkt == NULL;
+}
 
 template <class T>
 Fault
 TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
-    Request *req =
-        new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    _cpuId, /* thread ID */ 0);
+    const int asid = 0;
+    const int thread_id = 0;
+    bool do_access = true;  // flag to suppress cache access
+    const Addr pc = thread->readPC();
+
+    RequestPtr req;
+
+    int block_size = dcachePort.peerBlockSize();
+    int data_size = sizeof(T);
+
+    Addr second_addr = roundDown(addr + data_size - 1, block_size);
+
+    if (second_addr > addr) {
+        Fault fault;
+        Addr first_size = second_addr - addr;
+        Addr second_size = data_size - first_size;
+        // Make sure we'll only need two accesses.
+        assert(roundDown(second_addr + second_size - 1, block_size) == 
+                second_addr);
+
+        req = new Request(asid, addr, first_size,
+                          flags, pc, _cpuId, thread_id);
+        fault = thread->translateDataWriteReq(req);
+        if (fault != NoFault) {
+            delete req;
+            return fault;
+        }
+        RequestPtr second_req = new Request(asid, second_addr, second_size,
+                                            flags, pc, _cpuId, thread_id);
+        fault = thread->translateDataWriteReq(second_req);
+        if (fault != NoFault) {
+            delete req;
+            delete second_req;
+            return fault;
+        }
 
-    if (traceData) {
-        traceData->setAddr(req->getVaddr());
-    }
+        if (req->isLocked() || req->isSwap() || 
+                second_req->isLocked() || second_req->isSwap()) {
+            panic("LL/SCs and swaps can't be split.");
+        }
 
-    // translate to physical address
-    Fault fault = thread->translateDataWriteReq(req);
+        T * data_ptr = new T;
+
+        /*
+         * This is the big packet that will hold the data we've gotten so far,
+         * if any, and also act as the response we actually give to the
+         * instruction.
+         */
+        RequestPtr orig_req = 
+            new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id);
+        orig_req->setPhys(req->getPaddr(), data_size, flags);
+        PacketPtr big_pkt =
+            new Packet(orig_req, MemCmd::WriteResp, Packet::Broadcast);
+        big_pkt->dataDynamic<T>(data_ptr);
+        big_pkt->set(data);
+        SplitMainSenderState * main_send_state = new SplitMainSenderState;
+        big_pkt->senderState = main_send_state;
+        main_send_state->outstanding = 2;
+
+        assert(dcache_pkt == NULL);
+        // This is the packet we'll process now.
+        dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
+        dcache_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr);
+        dcache_pkt->senderState = new SplitFragmentSenderState(big_pkt, 0);
+
+        // This is the second half of the access we'll deal with later.
+        PacketPtr second_pkt =
+            new Packet(second_req, MemCmd::WriteReq, Packet::Broadcast);
+        second_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr + first_size);
+        second_pkt->senderState = new SplitFragmentSenderState(big_pkt, 1);
+        if (!handleWritePacket()) {
+            main_send_state->fragments[1] = second_pkt;
+        } else {
+            dcache_pkt = second_pkt;
+            handleWritePacket();
+        }
+    } else {
+        req = new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id);
+
+        // translate to physical address
+        Fault fault = thread->translateDataWriteReq(req);
+        if (fault != NoFault) {
+            delete req;
+            return fault;
+        }
 
-    // Now do the access.
-    if (fault == NoFault) {
         MemCmd cmd = MemCmd::WriteReq; // default
-        bool do_access = true;  // flag to suppress cache access
 
         if (req->isLocked()) {
             cmd = MemCmd::StoreCondReq;
@@ -401,38 +570,27 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         assert(dcache_pkt == NULL);
         dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
         dcache_pkt->allocate();
-        dcache_pkt->set(data);
-
-        if (do_access) {
-            if (req->isMmapedIpr()) {
-                Tick delay;
-                dcache_pkt->set(htog(data));
-                delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
-                new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
-                _status = DcacheWaitResponse;
-                dcache_pkt = NULL;
-            } else if (!dcachePort.sendTiming(dcache_pkt)) {
-                _status = DcacheRetry;
-            } else {
-                _status = DcacheWaitResponse;
-                // memory system takes ownership of packet
-                dcache_pkt = NULL;
-            }
-        }
-        // This will need a new way to tell if it's hooked up to a cache or not.
-        if (req->isUncacheable())
-            recordEvent("Uncached Write");
-    } else {
-        delete req;
+        if (req->isMmapedIpr())
+            dcache_pkt->set(htog(data));
+        else
+            dcache_pkt->set(data);
+
+        if (do_access)
+            handleWritePacket();
     }
 
     if (traceData) {
+        traceData->setAddr(req->getVaddr());
         traceData->setData(data);
     }
 
+    // This will need a new way to tell if it's hooked up to a cache or not.
+    if (req->isUncacheable())
+        recordEvent("Uncached Write");
+
     // If the write needs to have a fault on the access, consider calling
     // changeStatus() and changing it to "bad addr write" or something.
-    return fault;
+    return NoFault;
 }
 
 Fault
@@ -721,12 +879,38 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     // received a response from the dcache: complete the load or store
     // instruction
     assert(!pkt->isError());
-    assert(_status == DcacheWaitResponse);
-    _status = Running;
 
     numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
 
+    if (pkt->senderState) {
+        SplitFragmentSenderState * send_state =
+            dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
+        assert(send_state);
+        delete pkt->req;
+        delete pkt;
+        PacketPtr big_pkt = send_state->bigPkt;
+        delete send_state;
+        
+        SplitMainSenderState * main_send_state =
+            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
+        assert(main_send_state);
+        // Record the fact that this packet is no longer outstanding.
+        assert(main_send_state->outstanding != 0);
+        main_send_state->outstanding--;
+
+        if (main_send_state->outstanding) {
+            return;
+        } else {
+            delete main_send_state;
+            big_pkt->senderState = NULL;
+            pkt = big_pkt;
+        }
+    }
+
+    assert(_status == DcacheWaitResponse);
+    _status = Running;
+
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 
     // keep an instruction count
@@ -787,10 +971,11 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
         // delay processing of returned data until next CPU clock edge
         Tick next_tick = cpu->nextCycle(curTick);
 
-        if (next_tick == curTick)
+        if (next_tick == curTick) {
             cpu->completeDataAccess(pkt);
-        else
+        } else {
             tickEvent.schedule(pkt, next_tick);
+        }
 
         return true;
     }
@@ -820,7 +1005,36 @@ TimingSimpleCPU::DcachePort::recvRetry()
     assert(cpu->dcache_pkt != NULL);
     assert(cpu->_status == DcacheRetry);
     PacketPtr tmp = cpu->dcache_pkt;
-    if (sendTiming(tmp)) {
+    if (tmp->senderState) {
+        // This is a packet from a split access.
+        SplitFragmentSenderState * send_state =
+            dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
+        assert(send_state);
+        PacketPtr big_pkt = send_state->bigPkt;
+        
+        SplitMainSenderState * main_send_state =
+            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
+        assert(main_send_state);
+
+        if (sendTiming(tmp)) {
+            // If we were able to send without retrying, record that fact
+            // and try sending the other fragment.
+            send_state->clearFromParent();
+            int other_index = main_send_state->getPendingFragment();
+            if (other_index > 0) {
+                tmp = main_send_state->fragments[other_index];
+                cpu->dcache_pkt = tmp;
+                if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
+                        (big_pkt->isWrite() && cpu->handleWritePacket())) {
+                    main_send_state->fragments[other_index] = NULL;
+                }
+            } else {
+                cpu->_status = DcacheWaitResponse;
+                // memory system takes ownership of packet
+                cpu->dcache_pkt = NULL;
+            }
+        }
+    } else if (sendTiming(tmp)) {
         cpu->_status = DcacheWaitResponse;
         // memory system takes ownership of packet
         cpu->dcache_pkt = NULL;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 0fc9b3152..b641b1302 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -49,6 +49,63 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
   private:
 
+    /*
+     * If an access needs to be broken into fragments, currently at most two,
+     * the the following two classes are used as the sender state of the
+     * packets so the CPU can keep track of everything. In the main packet
+     * sender state, there's an array with a spot for each fragment. If a
+     * fragment has already been accepted by the CPU, aka isn't waiting for
+     * a retry, it's pointer is NULL. After each fragment has successfully
+     * been processed, the "outstanding" counter is decremented. Once the
+     * count is zero, the entire larger access is complete.
+     */
+    class SplitMainSenderState : public Packet::SenderState
+    {
+      public:
+        int outstanding;
+        PacketPtr fragments[2];
+
+        SplitMainSenderState()
+        {
+            fragments[0] = NULL;
+            fragments[1] = NULL;
+        }
+
+        int
+        getPendingFragment()
+        {
+            if (fragments[0]) {
+                return 0;
+            } else if (fragments[1]) {
+                return 1;
+            } else {
+                return -1;
+            }
+        }
+    };
+
+    class SplitFragmentSenderState : public Packet::SenderState
+    {
+      public:
+        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
+            bigPkt(_bigPkt), index(_index)
+        {}
+        PacketPtr bigPkt;
+        int index;
+
+        void
+        clearFromParent()
+        {
+            SplitMainSenderState * main_send_state =
+                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
+            main_send_state->fragments[index] = NULL;
+        }
+    };
+
+    bool handleReadPacket(PacketPtr pkt);
+    // This function always implicitly uses dcache_pkt.
+    bool handleWritePacket();
+
     class CpuPort : public Port
     {
       protected:
-- 
cgit v1.2.3


From 7a4d75bae31cfe2064fe0718c7f982f769659b3c Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 13 Nov 2008 23:30:37 -0800
Subject: CPU: Refactor read/write in the simple timing CPU.

---
 src/cpu/simple/timing.cc | 277 ++++++++++++++++++++---------------------------
 src/cpu/simple/timing.hh |  10 +-
 2 files changed, 119 insertions(+), 168 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5d37fa620..5da08db47 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -262,6 +262,72 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
     return dcache_pkt == NULL;
 }
 
+Fault
+TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
+        RequestPtr &req, Addr split_addr, uint8_t *data, bool read)
+{
+    Fault fault;
+    RequestPtr req1, req2;
+    assert(!req->isLocked() && !req->isSwap());
+    req->splitOnVaddr(split_addr, req1, req2);
+
+    pkt1 = pkt2 = NULL;
+    if ((fault = buildPacket(pkt1, req1, read)) != NoFault ||
+            (fault = buildPacket(pkt2, req2, read)) != NoFault) {
+        delete req;
+        delete pkt1;
+        req = NULL;
+        pkt1 = NULL;
+        return fault;
+    }
+
+    assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+
+    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
+    PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
+                               Packet::Broadcast);
+
+    pkt->dataDynamic<uint8_t>(data);
+    pkt1->dataStatic<uint8_t>(data);
+    pkt2->dataStatic<uint8_t>(data + req1->getSize());
+
+    SplitMainSenderState * main_send_state = new SplitMainSenderState;
+    pkt->senderState = main_send_state;
+    main_send_state->fragments[0] = pkt1;
+    main_send_state->fragments[1] = pkt2;
+    main_send_state->outstanding = 2;
+    pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
+    pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
+    return fault;
+}
+
+Fault
+TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
+{
+    Fault fault = read ? thread->translateDataReadReq(req) :
+                         thread->translateDataWriteReq(req);
+    MemCmd cmd;
+    if (fault != NoFault) {
+        delete req;
+        req = NULL;
+        pkt = NULL;
+        return fault;
+    } else if (read) {
+        cmd = MemCmd::ReadReq;
+        if (req->isLocked())
+            cmd = MemCmd::LoadLockedReq;
+    } else {
+        cmd = MemCmd::WriteReq;
+        if (req->isLocked()) {
+            cmd = MemCmd::StoreCondReq;
+        } else if (req->isSwap()) {
+            cmd = MemCmd::SwapReq;
+        }
+    }
+    pkt = new Packet(req, cmd, Packet::Broadcast);
+    return NoFault;
+}
+
 template <class T>
 Fault
 TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
@@ -270,91 +336,35 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
     const int asid = 0;
     const int thread_id = 0;
     const Addr pc = thread->readPC();
-
-    PacketPtr pkt;
-    RequestPtr req;
-
     int block_size = dcachePort.peerBlockSize();
     int data_size = sizeof(T);
 
-    Addr second_addr = roundDown(addr + data_size - 1, block_size);
-
-    if (second_addr > addr) {
-        Addr first_size = second_addr - addr;
-        Addr second_size = data_size - first_size;
-        // Make sure we'll only need two accesses.
-        assert(roundDown(second_addr + second_size - 1, block_size) ==
-                second_addr);
-
-        /*
-         * Do the translations. If something isn't going to work, find out
-         * before we waste time setting up anything else.
-         */
-        req = new Request(asid, addr, first_size,
-                          flags, pc, _cpuId, thread_id);
-        fault = thread->translateDataReadReq(req);
-        if (fault != NoFault) {
-            delete req;
-            return fault;
-        }
-        Request *second_req =
-            new Request(asid, second_addr, second_size,
-                        flags, pc, _cpuId, thread_id);
-        fault = thread->translateDataReadReq(second_req);
-        if (fault != NoFault) {
-            delete req;
-            delete second_req;
-            return fault;
-        }
-
-        T * data_ptr = new T;
-
-        /*
-         * This is the big packet that will hold the data we've gotten so far,
-         * if any, and also act as the response we actually give to the
-         * instruction.
-         */
-        Request *orig_req =
-            new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id);
-        orig_req->setPhys(req->getPaddr(), data_size, flags);
-        PacketPtr big_pkt =
-            new Packet(orig_req, MemCmd::ReadResp, Packet::Broadcast);
-        big_pkt->dataDynamic<T>(data_ptr);
-        SplitMainSenderState * main_send_state = new SplitMainSenderState;
-        big_pkt->senderState = main_send_state;
-        main_send_state->outstanding = 2;
-
-        // This is the packet we'll process now.
-        pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
-        pkt->dataStatic<uint8_t>((uint8_t *)data_ptr);
-        pkt->senderState = new SplitFragmentSenderState(big_pkt, 0);
-
-        // This is the second half of the access we'll deal with later.
-        PacketPtr second_pkt =
-            new Packet(second_req, MemCmd::ReadReq, Packet::Broadcast);
-        second_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr + first_size);
-        second_pkt->senderState = new SplitFragmentSenderState(big_pkt, 1);
-        if (!handleReadPacket(pkt)) {
-            main_send_state->fragments[1] = second_pkt;
-        } else {
-            handleReadPacket(second_pkt);
+    PacketPtr pkt;
+    RequestPtr req  = new Request(asid, addr, data_size,
+                                  flags, pc, _cpuId, thread_id);
+
+    Addr split_addr = roundDown(addr + data_size - 1, block_size);
+    assert(split_addr <= addr || split_addr - addr < block_size);
+
+    if (split_addr > addr) {
+        PacketPtr pkt1, pkt2;
+        this->buildSplitPacket(pkt1, pkt2, req,
+                split_addr, (uint8_t *)(new T), true);
+        if (handleReadPacket(pkt1)) {
+            SplitFragmentSenderState * send_state =
+                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+            send_state->clearFromParent();
+            if (handleReadPacket(pkt2)) {
+                send_state =
+                    dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+                send_state->clearFromParent();
+            }
         }
     } else {
-        req = new Request(asid, addr, data_size,
-                          flags, pc, _cpuId, thread_id);
-
-        // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
-
+        Fault fault = buildPacket(pkt, req, true);
         if (fault != NoFault) {
-            delete req;
             return fault;
         }
-
-        pkt = new Packet(req,
-                         (req->isLocked() ?
-                          MemCmd::LoadLockedReq : MemCmd::ReadReq),
-                          Packet::Broadcast);
         pkt->dataDynamic<T>(new T);
 
         handleReadPacket(pkt);
@@ -468,107 +478,50 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     const int asid = 0;
     const int thread_id = 0;
-    bool do_access = true;  // flag to suppress cache access
     const Addr pc = thread->readPC();
-
-    RequestPtr req;
-
     int block_size = dcachePort.peerBlockSize();
     int data_size = sizeof(T);
 
-    Addr second_addr = roundDown(addr + data_size - 1, block_size);
+    RequestPtr req = new Request(asid, addr, data_size,
+                                 flags, pc, _cpuId, thread_id);
 
-    if (second_addr > addr) {
-        Fault fault;
-        Addr first_size = second_addr - addr;
-        Addr second_size = data_size - first_size;
-        // Make sure we'll only need two accesses.
-        assert(roundDown(second_addr + second_size - 1, block_size) == 
-                second_addr);
+    Addr split_addr = roundDown(addr + data_size - 1, block_size);
+    assert(split_addr <= addr || split_addr - addr < block_size);
 
-        req = new Request(asid, addr, first_size,
-                          flags, pc, _cpuId, thread_id);
-        fault = thread->translateDataWriteReq(req);
-        if (fault != NoFault) {
-            delete req;
-            return fault;
-        }
-        RequestPtr second_req = new Request(asid, second_addr, second_size,
-                                            flags, pc, _cpuId, thread_id);
-        fault = thread->translateDataWriteReq(second_req);
-        if (fault != NoFault) {
-            delete req;
-            delete second_req;
+    if (split_addr > addr) {
+        PacketPtr pkt1, pkt2;
+        T *dataP = new T;
+        *dataP = data;
+        Fault fault = this->buildSplitPacket(pkt1, pkt2, req, split_addr,
+                                             (uint8_t *)dataP, false);
+        if (fault != NoFault)
             return fault;
-        }
-
-        if (req->isLocked() || req->isSwap() || 
-                second_req->isLocked() || second_req->isSwap()) {
-            panic("LL/SCs and swaps can't be split.");
-        }
-
-        T * data_ptr = new T;
-
-        /*
-         * This is the big packet that will hold the data we've gotten so far,
-         * if any, and also act as the response we actually give to the
-         * instruction.
-         */
-        RequestPtr orig_req = 
-            new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id);
-        orig_req->setPhys(req->getPaddr(), data_size, flags);
-        PacketPtr big_pkt =
-            new Packet(orig_req, MemCmd::WriteResp, Packet::Broadcast);
-        big_pkt->dataDynamic<T>(data_ptr);
-        big_pkt->set(data);
-        SplitMainSenderState * main_send_state = new SplitMainSenderState;
-        big_pkt->senderState = main_send_state;
-        main_send_state->outstanding = 2;
-
-        assert(dcache_pkt == NULL);
-        // This is the packet we'll process now.
-        dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
-        dcache_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr);
-        dcache_pkt->senderState = new SplitFragmentSenderState(big_pkt, 0);
-
-        // This is the second half of the access we'll deal with later.
-        PacketPtr second_pkt =
-            new Packet(second_req, MemCmd::WriteReq, Packet::Broadcast);
-        second_pkt->dataStatic<uint8_t>((uint8_t *)data_ptr + first_size);
-        second_pkt->senderState = new SplitFragmentSenderState(big_pkt, 1);
-        if (!handleWritePacket()) {
-            main_send_state->fragments[1] = second_pkt;
-        } else {
-            dcache_pkt = second_pkt;
-            handleWritePacket();
+        dcache_pkt = pkt1;
+        if (handleWritePacket()) {
+            SplitFragmentSenderState * send_state =
+                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+            send_state->clearFromParent();
+            dcache_pkt = pkt2;
+            if (handleReadPacket(pkt2)) {
+                send_state =
+                    dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+                send_state->clearFromParent();
+            }
         }
     } else {
-        req = new Request(asid, addr, data_size, flags, pc, _cpuId, thread_id);
+        bool do_access = true;  // flag to suppress cache access
 
-        // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
-        if (fault != NoFault) {
-            delete req;
+        Fault fault = buildPacket(dcache_pkt, req, false);
+        if (fault != NoFault)
             return fault;
-        }
-
-        MemCmd cmd = MemCmd::WriteReq; // default
 
         if (req->isLocked()) {
-            cmd = MemCmd::StoreCondReq;
             do_access = TheISA::handleLockedWrite(thread, req);
-        } else if (req->isSwap()) {
-            cmd = MemCmd::SwapReq;
-            if (req->isCondSwap()) {
-                assert(res);
-                req->setExtraData(*res);
-            }
+        } else if (req->isCondSwap()) {
+            assert(res);
+            req->setExtraData(*res);
         }
 
-        // Note: need to allocate dcache_pkt even if do_access is
-        // false, as it's used unconditionally to call completeAcc().
-        assert(dcache_pkt == NULL);
-        dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
         dcache_pkt->allocate();
         if (req->isMmapedIpr())
             dcache_pkt->set(htog(data));
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index b641b1302..c305d0361 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -65,12 +65,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
         int outstanding;
         PacketPtr fragments[2];
 
-        SplitMainSenderState()
-        {
-            fragments[0] = NULL;
-            fragments[1] = NULL;
-        }
-
         int
         getPendingFragment()
         {
@@ -102,6 +96,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
         }
     };
 
+    Fault buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr &req,
+            Addr split_addr, uint8_t *data, bool read);
+    Fault buildPacket(PacketPtr &pkt, RequestPtr &req, bool read);
+
     bool handleReadPacket(PacketPtr pkt);
     // This function always implicitly uses dcache_pkt.
     bool handleWritePacket();
-- 
cgit v1.2.3


From b0ab5c894d84d4522cae3a254158e47ba112909c Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 6 Jan 2009 22:34:18 -0800
Subject: Tracing: Make tracing aware of macro and micro ops.

---
 src/cpu/simple/base.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b3379cddb..3c154afb6 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -418,8 +418,9 @@ BaseSimpleCPU::preExecute()
     if(curStaticInst)
     {
 #if TRACING_ON
-        traceData = tracer->getInstRecord(curTick, tc, curStaticInst,
-                                         thread->readPC());
+        traceData = tracer->getInstRecord(curTick, tc,
+                curStaticInst, thread->readPC(),
+                curMacroStaticInst, thread->readMicroPC());
 
         DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
                 curStaticInst->getName(), curStaticInst->machInst);
-- 
cgit v1.2.3


From f0fb3ac060234ed5860c8d5bca3e84dbd8d30c36 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Sat, 24 Jan 2009 07:27:21 -0800
Subject: cpu: provide a wakeup mechanism that can be used to pull CPUs out of
 sleep. Make interrupts use the new wakeup method, and pull all of the
 interrupt stuff into the cpu base class so that only the wakeup code needs to
 be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms
 for waking and sleeping a little more sane, but I couldn't understand why the
 statistics were changing the way they were.  Maybe we'll try again some day.

---
 src/cpu/simple/base.cc | 11 +++++------
 src/cpu/simple/base.hh |  2 +-
 2 files changed, 6 insertions(+), 7 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 3c154afb6..89d9ce383 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -303,14 +303,13 @@ BaseSimpleCPU::dbg_vtophys(Addr addr)
 
 #if FULL_SYSTEM
 void
-BaseSimpleCPU::postInterrupt(int int_num, int index)
+BaseSimpleCPU::wakeup()
 {
-    BaseCPU::postInterrupt(int_num, index);
+    if (thread->status() != ThreadContext::Suspended)
+        return;
 
-    if (thread->status() == ThreadContext::Suspended) {
-                DPRINTF(Quiesce,"Suspended Processor awoke\n");
-        thread->activate();
-    }
+    DPRINTF(Quiesce,"Suspended Processor awoke\n");
+    thread->activate();
 }
 #endif // FULL_SYSTEM
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 6e72b8f6c..34d0f5954 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -98,7 +98,7 @@ class BaseSimpleCPU : public BaseCPU
     }
 
   public:
-    void postInterrupt(int int_num, int index);
+    void wakeup();
 
     void zero_fill_64(Addr addr) {
       static int warned = 0;
-- 
cgit v1.2.3


From 77209689499f2c843bebd9fca300fdd421277b15 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 1 Feb 2009 00:04:34 -0800
Subject: X86: Make sure the predecoder is cleared out for interrupts.

---
 src/cpu/simple/base.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 89d9ce383..9af5d0150 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -321,6 +321,7 @@ BaseSimpleCPU::checkForInterrupts()
         Fault interrupt = interrupts->getInterrupt(tc);
 
         if (interrupt != NoFault) {
+            predecoder.reset();
             interrupts->updateIntrInfo(tc);
             interrupt->invoke(tc);
         }
-- 
cgit v1.2.3


From 7b585114704532133c3aed01847fa534167018b3 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 1 Feb 2009 00:30:54 -0800
Subject: CPU: Don't always reset the micro pc on faults. Let the faults handle
 it.

---
 src/cpu/simple/base.cc | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 9af5d0150..b1a77247f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -472,8 +472,6 @@ BaseSimpleCPU::advancePC(Fault fault)
     if (fault != NoFault) {
         curMacroStaticInst = StaticInst::nullStaticInstPtr;
         predecoder.reset();
-        thread->setMicroPC(normalMicroPC(0));
-        thread->setNextMicroPC(normalMicroPC(1));
         fault->invoke(tc);
     } else {
         //If we're at the last micro op for this instruction
-- 
cgit v1.2.3


From a1aba01a02a8c1261120de83d8fbfd6624f0cb17 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:15:34 -0800
Subject: CPU: Get rid of translate... functions from various interface
 classes.

---
 src/cpu/simple/atomic.cc | 117 +---------------------------------------------
 src/cpu/simple/atomic.hh |   5 --
 src/cpu/simple/base.cc   |   2 +-
 src/cpu/simple/timing.cc | 118 ++++++++++++++++++++---------------------------
 src/cpu/simple/timing.hh |   6 ---
 5 files changed, 53 insertions(+), 195 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index feb8a7fc5..cd07a9fe3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
+        Fault fault = thread->dtb->translate(req, tc, false);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -370,61 +370,6 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     }
 }
 
-Fault
-AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr,
-        int size, unsigned flags)
-{
-    // use the CPU's statically allocated read request and packet objects
-    Request *req = &data_read_req;
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    //The block size of our peer.
-    int blockSize = dcachePort.peerBlockSize();
-    //The size of the data we're trying to read.
-    int dataSize = size;
-
-    bool firstTimeThrough = true;
-
-    //The address of the second part of this access if it needs to be split
-    //across a cache line boundary.
-    Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize);
-
-    if(secondAddr > vaddr)
-        dataSize = secondAddr - vaddr;
-
-    while(1) {
-        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
-
-        // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
-
-        //If there's a fault, return it
-        if (fault != NoFault)
-            return fault;
-
-        if (firstTimeThrough) {
-            paddr = req->getPaddr();
-            firstTimeThrough = false;
-        }
-
-        //If we don't need to access a second cache line, stop now.
-        if (secondAddr <= vaddr)
-            return fault;
-
-        /*
-         * Set up for accessing the second cache line.
-         */
-
-        //Adjust the size to get the remaining bytes.
-        dataSize = vaddr + size - secondAddr;
-        //And access the right address.
-        vaddr = secondAddr;
-    }
-}
-
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 template
@@ -507,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
+        Fault fault = thread->dtb->translate(req, tc, true);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -586,64 +531,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     }
 }
 
-Fault
-AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    // use the CPU's statically allocated write request and packet objects
-    Request *req = &data_write_req;
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    //The block size of our peer.
-    int blockSize = dcachePort.peerBlockSize();
-
-    //The address of the second part of this access if it needs to be split
-    //across a cache line boundary.
-    Addr secondAddr = roundDown(vaddr + size - 1, blockSize);
-
-    //The size of the data we're trying to read.
-    int dataSize = size;
-
-    bool firstTimeThrough = true;
-
-    if(secondAddr > vaddr)
-        dataSize = secondAddr - vaddr;
-
-    dcache_latency = 0;
-
-    while(1) {
-        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
-
-        // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
-
-        //If there's a fault or we don't need to access a second cache line,
-        //stop now.
-        if (fault != NoFault)
-            return fault;
-
-        if (firstTimeThrough) {
-            paddr = req->getPaddr();
-            firstTimeThrough = false;
-        }
-
-        if (secondAddr <= vaddr)
-            return fault;
-
-        /*
-         * Set up for accessing the second cache line.
-         */
-
-        //Adjust the size to get the remaining bytes.
-        dataSize = vaddr + size - secondAddr;
-        //And access the right address.
-        vaddr = secondAddr;
-    }
-}
-
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 24400df22..190097637 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -136,11 +136,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     template <class T>
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
-    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     /**
      * Print state of address in memory system via PrintReq (for
      * debugging).
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b1a77247f..f9fa8d835 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -347,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
     req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
 
-    Fault fault = thread->translateInstReq(req);
+    Fault fault = thread->itb->translate(req, tc);
 
     return fault;
 }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5da08db47..844eccc75 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -275,6 +275,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
     if ((fault = buildPacket(pkt1, req1, read)) != NoFault ||
             (fault = buildPacket(pkt2, req2, read)) != NoFault) {
         delete req;
+        delete req1;
         delete pkt1;
         req = NULL;
         pkt1 = NULL;
@@ -286,6 +287,15 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
     req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
     PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
                                Packet::Broadcast);
+    if (req->getFlags().isSet(Request::NO_ACCESS)) {
+        delete req1;
+        delete pkt1;
+        delete req2;
+        delete pkt2;
+        pkt1 = pkt;
+        pkt2 = NULL;
+        return NoFault;
+    }
 
     pkt->dataDynamic<uint8_t>(data);
     pkt1->dataStatic<uint8_t>(data);
@@ -304,8 +314,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 Fault
 TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
 {
-    Fault fault = read ? thread->translateDataReadReq(req) :
-                         thread->translateDataWriteReq(req);
+    Fault fault = thread->dtb->translate(req, tc, !read);
     MemCmd cmd;
     if (fault != NoFault) {
         delete req;
@@ -348,9 +357,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
     if (split_addr > addr) {
         PacketPtr pkt1, pkt2;
-        this->buildSplitPacket(pkt1, pkt2, req,
+        Fault fault = this->buildSplitPacket(pkt1, pkt2, req,
                 split_addr, (uint8_t *)(new T), true);
-        if (handleReadPacket(pkt1)) {
+        if (fault != NoFault)
+            return fault;
+        if (req->getFlags().isSet(Request::NO_ACCESS)) {
+            dcache_pkt = pkt1;
+        } else if (handleReadPacket(pkt1)) {
             SplitFragmentSenderState * send_state =
                 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
             send_state->clearFromParent();
@@ -365,9 +378,12 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
         if (fault != NoFault) {
             return fault;
         }
-        pkt->dataDynamic<T>(new T);
-
-        handleReadPacket(pkt);
+        if (req->getFlags().isSet(Request::NO_ACCESS)) {
+            dcache_pkt = pkt;
+        } else {
+            pkt->dataDynamic<T>(new T);
+            handleReadPacket(pkt);
+        }
     }
 
     if (traceData) {
@@ -382,26 +398,6 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
     return NoFault;
 }
 
-Fault
-TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    Fault fault = thread->translateDataWriteReq(req);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 template
@@ -497,15 +493,19 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (fault != NoFault)
             return fault;
         dcache_pkt = pkt1;
-        if (handleWritePacket()) {
-            SplitFragmentSenderState * send_state =
-                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
-            send_state->clearFromParent();
-            dcache_pkt = pkt2;
-            if (handleReadPacket(pkt2)) {
-                send_state =
-                    dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+        if (!req->getFlags().isSet(Request::NO_ACCESS)) {
+            if (handleWritePacket()) {
+                SplitFragmentSenderState * send_state =
+                    dynamic_cast<SplitFragmentSenderState *>(
+                            pkt1->senderState);
                 send_state->clearFromParent();
+                dcache_pkt = pkt2;
+                if (handleReadPacket(pkt2)) {
+                    send_state =
+                        dynamic_cast<SplitFragmentSenderState *>(
+                                pkt1->senderState);
+                    send_state->clearFromParent();
+                }
             }
         }
     } else {
@@ -515,21 +515,23 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (fault != NoFault)
             return fault;
 
-        if (req->isLocked()) {
-            do_access = TheISA::handleLockedWrite(thread, req);
-        } else if (req->isCondSwap()) {
-            assert(res);
-            req->setExtraData(*res);
-        }
+        if (!req->getFlags().isSet(Request::NO_ACCESS)) {
+            if (req->isLocked()) {
+                do_access = TheISA::handleLockedWrite(thread, req);
+            } else if (req->isCondSwap()) {
+                assert(res);
+                req->setExtraData(*res);
+            }
 
-        dcache_pkt->allocate();
-        if (req->isMmapedIpr())
-            dcache_pkt->set(htog(data));
-        else
-            dcache_pkt->set(data);
+            dcache_pkt->allocate();
+            if (req->isMmapedIpr())
+                dcache_pkt->set(htog(data));
+            else
+                dcache_pkt->set(data);
 
-        if (do_access)
-            handleWritePacket();
+            if (do_access)
+                handleWritePacket();
+        }
     }
 
     if (traceData) {
@@ -546,26 +548,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     return NoFault;
 }
 
-Fault
-TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    Fault fault = thread->translateDataWriteReq(req);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 template
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index c305d0361..0a639a627 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -224,15 +224,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
     template <class T>
     Fault read(Addr addr, T &data, unsigned flags);
 
-    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     template <class T>
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
-    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     void fetch();
     void completeIfetch(PacketPtr );
     void completeDataAccess(PacketPtr );
-- 
cgit v1.2.3


From 5605079b1f20bc7f6a4a80c8d1e4daabe7125270 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:15:44 -0800
Subject: ISA: Replace the translate functions in the TLBs with
 translateAtomic.

---
 src/cpu/simple/atomic.cc | 4 ++--
 src/cpu/simple/base.cc   | 2 +-
 src/cpu/simple/timing.cc | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index cd07a9fe3..7a1cf71c4 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->dtb->translate(req, tc, false);
+        Fault fault = thread->dtb->translateAtomic(req, tc, false);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->dtb->translate(req, tc, true);
+        Fault fault = thread->dtb->translateAtomic(req, tc, true);
 
         // Now do the access.
         if (fault == NoFault) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f9fa8d835..ddeb9a7c8 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -347,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
     req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
 
-    Fault fault = thread->itb->translate(req, tc);
+    Fault fault = thread->itb->translateAtomic(req, tc);
 
     return fault;
 }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 844eccc75..65222266e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -314,7 +314,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 Fault
 TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
 {
-    Fault fault = thread->dtb->translate(req, tc, !read);
+    Fault fault = thread->dtb->translateAtomic(req, tc, !read);
     MemCmd cmd;
     if (fault != NoFault) {
         delete req;
-- 
cgit v1.2.3


From 6ed47e94644f854baa33d1e9f367cc9eebd99abf Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:16:15 -0800
Subject: CPU: Implement translateTiming which defers to translateAtomic, and
 convert the timing simple CPU to use it.

---
 src/cpu/simple/atomic.cc |   6 +-
 src/cpu/simple/base.cc   |   6 +-
 src/cpu/simple/base.hh   |   4 +-
 src/cpu/simple/timing.cc | 364 ++++++++++++++++++++++++++---------------------
 src/cpu/simple/timing.hh | 114 ++++++++++++++-
 5 files changed, 321 insertions(+), 173 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 7a1cf71c4..2ada12b8d 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -607,8 +607,10 @@ AtomicSimpleCPU::tick()
         Fault fault = NoFault;
 
         bool fromRom = isRomMicroPC(thread->readMicroPC());
-        if (!fromRom)
-            fault = setupFetchRequest(&ifetch_req);
+        if (!fromRom) {
+            setupFetchRequest(&ifetch_req);
+            fault = thread->itb->translateAtomic(&ifetch_req, tc);
+        }
 
         if (fault == NoFault) {
             Tick icache_latency = 0;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index ddeb9a7c8..9372ff43d 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -330,7 +330,7 @@ BaseSimpleCPU::checkForInterrupts()
 }
 
 
-Fault
+void
 BaseSimpleCPU::setupFetchRequest(Request *req)
 {
     Addr threadPC = thread->readPC();
@@ -346,10 +346,6 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
 
     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
     req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
-
-    Fault fault = thread->itb->translateAtomic(req, tc);
-
-    return fault;
 }
 
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 34d0f5954..d2ccc0ff1 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -125,9 +125,11 @@ class BaseSimpleCPU : public BaseCPU
     enum Status {
         Idle,
         Running,
+        ITBWaitResponse,
         IcacheRetry,
         IcacheWaitResponse,
         IcacheWaitSwitch,
+        DTBWaitResponse,
         DcacheRetry,
         DcacheWaitResponse,
         DcacheWaitSwitch,
@@ -160,7 +162,7 @@ class BaseSimpleCPU : public BaseCPU
     bool stayAtPC;
 
     void checkForInterrupts();
-    Fault setupFetchRequest(Request *req);
+    void setupFetchRequest(Request *req);
     void preExecute();
     void postExecute();
     void advancePC(Fault fault);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 65222266e..3f5778138 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -104,7 +104,8 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 }
 
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
-    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), fetchEvent(this)
+    : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
+    dcachePort(this, p->clock), fetchEvent(this)
 {
     _status = Idle;
 
@@ -262,66 +263,123 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
     return dcache_pkt == NULL;
 }
 
-Fault
-TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
-        RequestPtr &req, Addr split_addr, uint8_t *data, bool read)
+void
+TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
+        uint8_t *data, uint64_t *res, bool read)
 {
-    Fault fault;
-    RequestPtr req1, req2;
-    assert(!req->isLocked() && !req->isSwap());
-    req->splitOnVaddr(split_addr, req1, req2);
-
-    pkt1 = pkt2 = NULL;
-    if ((fault = buildPacket(pkt1, req1, read)) != NoFault ||
-            (fault = buildPacket(pkt2, req2, read)) != NoFault) {
+    _status = Running;
+    if (fault != NoFault) {
+        delete data;
         delete req;
-        delete req1;
-        delete pkt1;
-        req = NULL;
-        pkt1 = NULL;
-        return fault;
+
+        translationFault(fault);
+        return;
     }
+    PacketPtr pkt;
+    buildPacket(pkt, req, read);
+    pkt->dataDynamic<uint8_t>(data);
+    if (req->getFlags().isSet(Request::NO_ACCESS)) {
+        assert(!dcache_pkt);
+        pkt->makeResponse();
+        completeDataAccess(pkt);
+    } else if (read) {
+        handleReadPacket(pkt);
+    } else {
+        bool do_access = true;  // flag to suppress cache access
 
-    assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+        if (req->isLocked()) {
+            do_access = TheISA::handleLockedWrite(thread, req);
+        } else if (req->isCondSwap()) {
+            assert(res);
+            req->setExtraData(*res);
+        }
 
-    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
-    PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
-                               Packet::Broadcast);
-    if (req->getFlags().isSet(Request::NO_ACCESS)) {
+        if (do_access) {
+            dcache_pkt = pkt;
+            handleWritePacket();
+        } else {
+            _status = DcacheWaitResponse;
+            completeDataAccess(pkt);
+        }
+    }
+}
+
+void
+TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
+        RequestPtr req1, RequestPtr req2, RequestPtr req,
+        uint8_t *data, bool read)
+{
+    _status = Running;
+    if (fault1 != NoFault || fault2 != NoFault) {
+        delete data;
         delete req1;
-        delete pkt1;
         delete req2;
-        delete pkt2;
-        pkt1 = pkt;
-        pkt2 = NULL;
-        return NoFault;
+        if (fault1 != NoFault)
+            translationFault(fault1);
+        else if (fault2 != NoFault)
+            translationFault(fault2);
+        return;
+    }
+    PacketPtr pkt1, pkt2;
+    buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
+    if (req->getFlags().isSet(Request::NO_ACCESS)) {
+        assert(!dcache_pkt);
+        pkt1->makeResponse();
+        completeDataAccess(pkt1);
+    } else if (read) {
+        if (handleReadPacket(pkt1)) {
+            SplitFragmentSenderState * send_state =
+                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+            send_state->clearFromParent();
+            if (handleReadPacket(pkt2)) {
+                send_state = dynamic_cast<SplitFragmentSenderState *>(
+                        pkt1->senderState);
+                send_state->clearFromParent();
+            }
+        }
+    } else {
+        dcache_pkt = pkt1;
+        if (handleWritePacket()) {
+            SplitFragmentSenderState * send_state =
+                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+            send_state->clearFromParent();
+            dcache_pkt = pkt2;
+            if (handleWritePacket()) {
+                send_state = dynamic_cast<SplitFragmentSenderState *>(
+                        pkt1->senderState);
+                send_state->clearFromParent();
+            }
+        }
     }
+}
 
-    pkt->dataDynamic<uint8_t>(data);
-    pkt1->dataStatic<uint8_t>(data);
-    pkt2->dataStatic<uint8_t>(data + req1->getSize());
+void
+TimingSimpleCPU::translationFault(Fault fault)
+{
+    numCycles += tickToCycles(curTick - previousTick);
+    previousTick = curTick;
 
-    SplitMainSenderState * main_send_state = new SplitMainSenderState;
-    pkt->senderState = main_send_state;
-    main_send_state->fragments[0] = pkt1;
-    main_send_state->fragments[1] = pkt2;
-    main_send_state->outstanding = 2;
-    pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
-    pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
-    return fault;
+    if (traceData) {
+        // Since there was a fault, we shouldn't trace this instruction.
+        delete traceData;
+        traceData = NULL;
+    }
+
+    postExecute();
+
+    if (getState() == SimObject::Draining) {
+        advancePC(fault);
+        completeDrain();
+    } else {
+        advanceInst(fault);
+    }
 }
 
-Fault
-TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
+void
+TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
 {
-    Fault fault = thread->dtb->translateAtomic(req, tc, !read);
     MemCmd cmd;
-    if (fault != NoFault) {
-        delete req;
-        req = NULL;
-        pkt = NULL;
-        return fault;
-    } else if (read) {
+    if (read) {
         cmd = MemCmd::ReadReq;
         if (req->isLocked())
             cmd = MemCmd::LoadLockedReq;
@@ -334,7 +392,40 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
         }
     }
     pkt = new Packet(req, cmd, Packet::Broadcast);
-    return NoFault;
+}
+
+void
+TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
+        RequestPtr req1, RequestPtr req2, RequestPtr req,
+        uint8_t *data, bool read)
+{
+    pkt1 = pkt2 = NULL;
+
+    assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+
+    if (req->getFlags().isSet(Request::NO_ACCESS)) {
+        buildPacket(pkt1, req, read);
+        return;
+    }
+
+    buildPacket(pkt1, req1, read);
+    buildPacket(pkt2, req2, read);
+
+    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
+    PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
+                               Packet::Broadcast);
+
+    pkt->dataDynamic<uint8_t>(data);
+    pkt1->dataStatic<uint8_t>(data);
+    pkt2->dataStatic<uint8_t>(data + req1->getSize());
+
+    SplitMainSenderState * main_send_state = new SplitMainSenderState;
+    pkt->senderState = main_send_state;
+    main_send_state->fragments[0] = pkt1;
+    main_send_state->fragments[1] = pkt2;
+    main_send_state->outstanding = 2;
+    pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
+    pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
 }
 
 template <class T>
@@ -348,42 +439,30 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
     int block_size = dcachePort.peerBlockSize();
     int data_size = sizeof(T);
 
-    PacketPtr pkt;
     RequestPtr req  = new Request(asid, addr, data_size,
                                   flags, pc, _cpuId, thread_id);
 
     Addr split_addr = roundDown(addr + data_size - 1, block_size);
     assert(split_addr <= addr || split_addr - addr < block_size);
 
+
+    _status = DTBWaitResponse;
     if (split_addr > addr) {
-        PacketPtr pkt1, pkt2;
-        Fault fault = this->buildSplitPacket(pkt1, pkt2, req,
-                split_addr, (uint8_t *)(new T), true);
-        if (fault != NoFault)
-            return fault;
-        if (req->getFlags().isSet(Request::NO_ACCESS)) {
-            dcache_pkt = pkt1;
-        } else if (handleReadPacket(pkt1)) {
-            SplitFragmentSenderState * send_state =
-                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
-            send_state->clearFromParent();
-            if (handleReadPacket(pkt2)) {
-                send_state =
-                    dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
-                send_state->clearFromParent();
-            }
-        }
+        RequestPtr req1, req2;
+        assert(!req->isLocked() && !req->isSwap());
+        req->splitOnVaddr(split_addr, req1, req2);
+
+        typedef SplitDataTranslation::WholeTranslationState WholeState;
+        WholeState *state = new WholeState(req1, req2, req,
+                (uint8_t *)(new T), true);
+        thread->dtb->translateTiming(req1, tc,
+                new SplitDataTranslation(this, 0, state), false);
+        thread->dtb->translateTiming(req2, tc,
+                new SplitDataTranslation(this, 1, state), false);
     } else {
-        Fault fault = buildPacket(pkt, req, true);
-        if (fault != NoFault) {
-            return fault;
-        }
-        if (req->getFlags().isSet(Request::NO_ACCESS)) {
-            dcache_pkt = pkt;
-        } else {
-            pkt->dataDynamic<T>(new T);
-            handleReadPacket(pkt);
-        }
+        thread->dtb->translateTiming(req, tc,
+                new DataTranslation(this, (uint8_t *)(new T), NULL, true),
+                false);
     }
 
     if (traceData) {
@@ -484,54 +563,25 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     Addr split_addr = roundDown(addr + data_size - 1, block_size);
     assert(split_addr <= addr || split_addr - addr < block_size);
 
+    T *dataP = new T;
+    *dataP = TheISA::gtoh(data);
+    _status = DTBWaitResponse;
     if (split_addr > addr) {
-        PacketPtr pkt1, pkt2;
-        T *dataP = new T;
-        *dataP = data;
-        Fault fault = this->buildSplitPacket(pkt1, pkt2, req, split_addr,
-                                             (uint8_t *)dataP, false);
-        if (fault != NoFault)
-            return fault;
-        dcache_pkt = pkt1;
-        if (!req->getFlags().isSet(Request::NO_ACCESS)) {
-            if (handleWritePacket()) {
-                SplitFragmentSenderState * send_state =
-                    dynamic_cast<SplitFragmentSenderState *>(
-                            pkt1->senderState);
-                send_state->clearFromParent();
-                dcache_pkt = pkt2;
-                if (handleReadPacket(pkt2)) {
-                    send_state =
-                        dynamic_cast<SplitFragmentSenderState *>(
-                                pkt1->senderState);
-                    send_state->clearFromParent();
-                }
-            }
-        }
+        RequestPtr req1, req2;
+        assert(!req->isLocked() && !req->isSwap());
+        req->splitOnVaddr(split_addr, req1, req2);
+
+        typedef SplitDataTranslation::WholeTranslationState WholeState;
+        WholeState *state = new WholeState(req1, req2, req,
+                (uint8_t *)dataP, false);
+        thread->dtb->translateTiming(req1, tc,
+                new SplitDataTranslation(this, 0, state), true);
+        thread->dtb->translateTiming(req2, tc,
+                new SplitDataTranslation(this, 1, state), true);
     } else {
-        bool do_access = true;  // flag to suppress cache access
-
-        Fault fault = buildPacket(dcache_pkt, req, false);
-        if (fault != NoFault)
-            return fault;
-
-        if (!req->getFlags().isSet(Request::NO_ACCESS)) {
-            if (req->isLocked()) {
-                do_access = TheISA::handleLockedWrite(thread, req);
-            } else if (req->isCondSwap()) {
-                assert(res);
-                req->setExtraData(*res);
-            }
-
-            dcache_pkt->allocate();
-            if (req->isMmapedIpr())
-                dcache_pkt->set(htog(data));
-            else
-                dcache_pkt->set(data);
-
-            if (do_access)
-                handleWritePacket();
-        }
+        thread->dtb->translateTiming(req, tc,
+                new DataTranslation(this, (uint8_t *)dataP, res, false),
+                true);
     }
 
     if (traceData) {
@@ -620,30 +670,39 @@ TimingSimpleCPU::fetch()
     if (!fromRom) {
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
-        Fault fault = setupFetchRequest(ifetch_req);
+        setupFetchRequest(ifetch_req);
+        thread->itb->translateTiming(ifetch_req, tc,
+                &fetchTranslation);
+    } else {
+        _status = IcacheWaitResponse;
+        completeIfetch(NULL);
 
-        ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
+        numCycles += tickToCycles(curTick - previousTick);
+        previousTick = curTick;
+    }
+}
+
+
+void
+TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
+{
+    if (fault == NoFault) {
+        ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
         ifetch_pkt->dataStatic(&inst);
 
-        if (fault == NoFault) {
-            if (!icachePort.sendTiming(ifetch_pkt)) {
-                // Need to wait for retry
-                _status = IcacheRetry;
-            } else {
-                // Need to wait for cache to respond
-                _status = IcacheWaitResponse;
-                // ownership of packet transferred to memory system
-                ifetch_pkt = NULL;
-            }
+        if (!icachePort.sendTiming(ifetch_pkt)) {
+            // Need to wait for retry
+            _status = IcacheRetry;
         } else {
-            delete ifetch_req;
-            delete ifetch_pkt;
-            // fetch fault: advance directly to next instruction (fault handler)
-            advanceInst(fault);
+            // Need to wait for cache to respond
+            _status = IcacheWaitResponse;
+            // ownership of packet transferred to memory system
+            ifetch_pkt = NULL;
         }
     } else {
-        _status = IcacheWaitResponse;
-        completeIfetch(NULL);
+        delete req;
+        // fetch fault: advance directly to next instruction (fault handler)
+        advanceInst(fault);
     }
 
     numCycles += tickToCycles(curTick - previousTick);
@@ -699,28 +758,11 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
         Fault fault = curStaticInst->initiateAcc(this, traceData);
         if (_status != Running) {
             // instruction will complete in dcache response callback
-            assert(_status == DcacheWaitResponse || _status == DcacheRetry);
+            assert(_status == DcacheWaitResponse ||
+                    _status == DcacheRetry || DTBWaitResponse);
             assert(fault == NoFault);
         } else {
-            if (fault == NoFault) {
-                // Note that ARM can have NULL packets if the instruction gets
-                // squashed due to predication
-                // early fail on store conditional: complete now
-                assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
-
-                fault = curStaticInst->completeAcc(dcache_pkt, this,
-                                                   traceData);
-                if (dcache_pkt != NULL)
-                {
-                    delete dcache_pkt->req;
-                    delete dcache_pkt;
-                    dcache_pkt = NULL;
-                }
-
-                // keep an instruction count
-                if (fault == NoFault)
-                    countInst();
-            } else if (traceData) {
+            if (fault != NoFault && traceData) {
                 // If there was a fault, we shouldn't trace this instruction.
                 delete traceData;
                 traceData = NULL;
@@ -843,7 +885,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
         }
     }
 
-    assert(_status == DcacheWaitResponse);
+    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
     _status = Running;
 
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 0a639a627..a02ec48c9 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -96,9 +96,114 @@ class TimingSimpleCPU : public BaseSimpleCPU
         }
     };
 
-    Fault buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr &req,
-            Addr split_addr, uint8_t *data, bool read);
-    Fault buildPacket(PacketPtr &pkt, RequestPtr &req, bool read);
+    class FetchTranslation : public BaseTLB::Translation
+    {
+      protected:
+        TimingSimpleCPU *cpu;
+
+      public:
+        FetchTranslation(TimingSimpleCPU *_cpu) : cpu(_cpu)
+        {}
+
+        void finish(Fault fault, RequestPtr req,
+                ThreadContext *tc, bool write)
+        {
+            cpu->sendFetch(fault, req, tc);
+        }
+    };
+    FetchTranslation fetchTranslation;
+
+    class DataTranslation : public BaseTLB::Translation
+    {
+      protected:
+        TimingSimpleCPU *cpu;
+        uint8_t *data;
+        uint64_t *res;
+        bool read;
+
+      public:
+        DataTranslation(TimingSimpleCPU *_cpu,
+                uint8_t *_data, uint64_t *_res, bool _read) :
+            cpu(_cpu), data(_data), res(_res), read(_read)
+        {}
+
+        void
+        finish(Fault fault, RequestPtr req,
+                ThreadContext *tc, bool write)
+        {
+            cpu->sendData(fault, req, data, res, read);
+            delete this;
+        }
+    };
+
+    class SplitDataTranslation : public BaseTLB::Translation
+    {
+      public:
+        struct WholeTranslationState
+        {
+          public:
+            int outstanding;
+            RequestPtr requests[2];
+            RequestPtr mainReq;
+            Fault faults[2];
+            uint8_t *data;
+            bool read;
+
+            WholeTranslationState(RequestPtr req1, RequestPtr req2,
+                    RequestPtr main, uint8_t *_data, bool _read)
+            {
+                outstanding = 2;
+                requests[0] = req1;
+                requests[1] = req2;
+                mainReq = main;
+                faults[0] = faults[1] = NoFault;
+                data = _data;
+                read = _read;
+            }
+        };
+
+        TimingSimpleCPU *cpu;
+        int index;
+        WholeTranslationState *state;
+
+        SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
+                WholeTranslationState *_state) :
+            cpu(_cpu), index(_index), state(_state)
+        {}
+
+        void
+        finish(Fault fault, RequestPtr req,
+                ThreadContext *tc, bool write)
+        {
+            assert(state);
+            assert(state->outstanding);
+            state->faults[index] = fault;
+            if (--state->outstanding == 0) {
+                cpu->sendSplitData(state->faults[0],
+                                   state->faults[1],
+                                   state->requests[0],
+                                   state->requests[1],
+                                   state->mainReq,
+                                   state->data,
+                                   state->read);
+                delete state;
+            }
+            delete this;
+        }
+    };
+
+    void sendData(Fault fault, RequestPtr req,
+            uint8_t *data, uint64_t *res, bool read);
+    void sendSplitData(Fault fault1, Fault fault2,
+            RequestPtr req1, RequestPtr req2, RequestPtr req,
+            uint8_t *data, bool read);
+
+    void translationFault(Fault fault);
+
+    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
+    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
+            RequestPtr req1, RequestPtr req2, RequestPtr req,
+            uint8_t *data, bool read);
 
     bool handleReadPacket(PacketPtr pkt);
     // This function always implicitly uses dcache_pkt.
@@ -228,8 +333,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
     void fetch();
+    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
     void completeIfetch(PacketPtr );
-    void completeDataAccess(PacketPtr );
+    void completeDataAccess(PacketPtr pkt);
     void advanceInst(Fault fault);
 
     /**
-- 
cgit v1.2.3


From da61c4b3ee4571d43f7133640eeda2cf51e21cd9 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 10:18:36 -0800
Subject: CPU: Don't fetch when executing a macroop. If the CPL changes mid
 macroop, the end of the instruction might not be priveleged enough to execute
 the beginning.

---
 src/cpu/simple/atomic.cc | 4 ++--
 src/cpu/simple/timing.cc | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 2ada12b8d..acda552d9 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -607,7 +607,7 @@ AtomicSimpleCPU::tick()
         Fault fault = NoFault;
 
         bool fromRom = isRomMicroPC(thread->readMicroPC());
-        if (!fromRom) {
+        if (!fromRom && !curMacroStaticInst) {
             setupFetchRequest(&ifetch_req);
             fault = thread->itb->translateAtomic(&ifetch_req, tc);
         }
@@ -617,7 +617,7 @@ AtomicSimpleCPU::tick()
             bool icache_access = false;
             dcache_access = false; // assume no dcache access
 
-            if (!fromRom) {
+            if (!fromRom && !curMacroStaticInst) {
                 // This is commented out because the predecoder would act like
                 // a tiny cache otherwise. It wouldn't be flushed when needed
                 // like the I cache. It should be flushed, and when that works
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 3f5778138..f398365d3 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -667,7 +667,7 @@ TimingSimpleCPU::fetch()
 
     bool fromRom = isRomMicroPC(thread->readMicroPC());
 
-    if (!fromRom) {
+    if (!fromRom && !curMacroStaticInst) {
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);
-- 
cgit v1.2.3


From d447ccb2c61a9225e5663ac29c999ac0a52a412f Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Thu, 26 Feb 2009 19:29:17 -0500
Subject: CPA: Add code to automatically record function symbols as CPU
 executes.

---
 src/cpu/simple/base.cc | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 9372ff43d..348d2392f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -31,6 +31,7 @@
 #include "arch/utility.hh"
 #include "arch/faults.hh"
 #include "base/cprintf.hh"
+#include "base/cp_annotate.hh"
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
@@ -450,6 +451,10 @@ BaseSimpleCPU::postExecute()
         comLoadEventQueue[0]->serviceEvents(numLoad);
     }
 
+    if (CPA::available()) {
+        CPA::cpa()->swAutoBegin(tc, thread->readNextPC());
+    }
+
     traceFunctions(thread->readPC());
 
     if (traceData) {
-- 
cgit v1.2.3


From cc95b5739097e31fdaa36a3ff443861969e338b1 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Thu, 5 Mar 2009 19:09:53 -0800
Subject: stats: Fix all stats usages to deal with template fixes

---
 src/cpu/simple/base.hh | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index d2ccc0ff1..e80606388 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -177,7 +177,7 @@ class BaseSimpleCPU : public BaseCPU
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;
-    Stats::Scalar<> numInsts;
+    Stats::Scalar numInsts;
 
     void countInst()
     {
@@ -196,30 +196,30 @@ class BaseSimpleCPU : public BaseCPU
     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 
     // number of simulated memory references
-    Stats::Scalar<> numMemRefs;
+    Stats::Scalar numMemRefs;
 
     // number of simulated loads
     Counter numLoad;
     Counter startNumLoad;
 
     // number of idle cycles
-    Stats::Average<> notIdleFraction;
+    Stats::Average notIdleFraction;
     Stats::Formula idleFraction;
 
     // number of cycles stalled for I-cache responses
-    Stats::Scalar<> icacheStallCycles;
+    Stats::Scalar icacheStallCycles;
     Counter lastIcacheStall;
 
     // number of cycles stalled for I-cache retries
-    Stats::Scalar<> icacheRetryCycles;
+    Stats::Scalar icacheRetryCycles;
     Counter lastIcacheRetry;
 
     // number of cycles stalled for D-cache responses
-    Stats::Scalar<> dcacheStallCycles;
+    Stats::Scalar dcacheStallCycles;
     Counter lastDcacheStall;
 
     // number of cycles stalled for D-cache retries
-    Stats::Scalar<> dcacheRetryCycles;
+    Stats::Scalar dcacheRetryCycles;
     Counter lastDcacheRetry;
 
     virtual void serialize(std::ostream &os);
-- 
cgit v1.2.3


From 61ff48a1f834b7335c2ae615a1f855995cfab335 Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Wed, 11 Mar 2009 23:05:24 -0700
Subject: cpu: fix minor endian issue with trace output (no functional change)

---
 src/cpu/simple/atomic.cc | 2 +-
 src/cpu/simple/timing.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/cpu/simple')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index acda552d9..17f93c882 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -513,7 +513,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
             // calling changeStatus() and changing it to "bad addr write"
             // or something.
             if (traceData) {
-                traceData->setData(data);
+                traceData->setData(gtoh(data));
             }
             return fault;
         }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f398365d3..a8f86f8d2 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -564,7 +564,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     assert(split_addr <= addr || split_addr - addr < block_size);
 
     T *dataP = new T;
-    *dataP = TheISA::gtoh(data);
+    *dataP = TheISA::htog(data);
     _status = DTBWaitResponse;
     if (split_addr > addr) {
         RequestPtr req1, req2;
-- 
cgit v1.2.3