From da61c4b3ee4571d43f7133640eeda2cf51e21cd9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:18:36 -0800 Subject: CPU: Don't fetch when executing a macroop. If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning. --- src/cpu/simple/atomic.cc | 4 ++-- src/cpu/simple/timing.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 2ada12b8d..acda552d9 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -607,7 +607,7 @@ AtomicSimpleCPU::tick() Fault fault = NoFault; bool fromRom = isRomMicroPC(thread->readMicroPC()); - if (!fromRom) { + if (!fromRom && !curMacroStaticInst) { setupFetchRequest(&ifetch_req); fault = thread->itb->translateAtomic(&ifetch_req, tc); } @@ -617,7 +617,7 @@ AtomicSimpleCPU::tick() bool icache_access = false; dcache_access = false; // assume no dcache access - if (!fromRom) { + if (!fromRom && !curMacroStaticInst) { // This is commented out because the predecoder would act like // a tiny cache otherwise. It wouldn't be flushed when needed // like the I cache. It should be flushed, and when that works diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 3f5778138..f398365d3 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -667,7 +667,7 @@ TimingSimpleCPU::fetch() bool fromRom = isRomMicroPC(thread->readMicroPC()); - if (!fromRom) { + if (!fromRom && !curMacroStaticInst) { Request *ifetch_req = new Request(); ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); setupFetchRequest(ifetch_req); -- cgit v1.2.3