From e8381142b061fbdf2f22d958f1c7559e9ffb3bd8 Mon Sep 17 00:00:00 2001 From: Dam Sunwoo Date: Mon, 22 Apr 2013 13:20:31 -0400 Subject: sim: separate nextCycle() and clockEdge() in clockedObjects Previously, nextCycle() could return the *current* cycle if the current tick was already aligned with the clock edge. This behavior is not only confusing (not quite what the function name implies), but also caused problems in the drainResume() function. When exiting/re-entering the sim loop (e.g., to take checkpoints), the CPUs will drain and resume. Due to the previous behavior of nextCycle(), the CPU tick events were being rescheduled in the same ticks that were already processed before draining. This caused divergence from runs that did not exit/re-entered the sim loop. (Initially a cycle difference, but a significant impact later on.) This patch separates out the two behaviors (nextCycle() and clockEdge()), uses nextCycle() in drainResume, and uses clockEdge() everywhere else. Nothing (other than name) should change except for the drainResume timing. --- src/cpu/simple/timing.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index ab4ea9256..1f453ca63 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -120,7 +120,7 @@ TimingSimpleCPU::drain(DrainManager *drain_manager) // succeed on the first attempt. We need to reschedule it if // the CPU is waiting for a microcode routine to complete. if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled()) - schedule(fetchEvent, nextCycle()); + schedule(fetchEvent, clockEdge()); return 1; } @@ -616,7 +616,7 @@ TimingSimpleCPU::advanceInst(Fault fault) if (fault != NoFault) { advancePC(fault); DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n"); - reschedule(fetchEvent, nextCycle(), true); + reschedule(fetchEvent, clockEdge(), true); _status = Faulting; return; } @@ -715,7 +715,7 @@ TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) { DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); // delay processing of returned data until next CPU clock edge - Tick next_tick = cpu->nextCycle(); + Tick next_tick = cpu->clockEdge(); if (next_tick == curTick()) cpu->completeIfetch(pkt); @@ -807,7 +807,7 @@ bool TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) { // delay processing of returned data until next CPU clock edge - Tick next_tick = cpu->nextCycle(); + Tick next_tick = cpu->clockEdge(); if (next_tick == curTick()) { cpu->completeDataAccess(pkt); -- cgit v1.2.3