From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 4 Jun 2018 09:40:19 +0100 Subject: misc: Using smart pointers for memory Requests This patch is changing the underlying type for RequestPtr from Request* to shared_ptr. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/cpu/simple/atomic.cc | 27 +++++++++++++++------------ src/cpu/simple/atomic.hh | 6 +++--- src/cpu/simple/base.cc | 2 +- src/cpu/simple/base.hh | 2 +- src/cpu/simple/timing.cc | 32 +++++++++++++++----------------- src/cpu/simple/timing.hh | 16 ++++++++++------ 6 files changed, 45 insertions(+), 40 deletions(-) (limited to 'src/cpu/simple') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 0e7c59f6a..040d1dbf9 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -69,9 +69,9 @@ AtomicSimpleCPU::init() BaseSimpleCPU::init(); int cid = threadContexts[0]->contextId(); - ifetch_req.setContext(cid); - data_read_req.setContext(cid); - data_write_req.setContext(cid); + ifetch_req->setContext(cid); + data_read_req->setContext(cid); + data_write_req->setContext(cid); } AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) @@ -87,6 +87,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) ppCommit(nullptr) { _status = Idle; + ifetch_req = std::make_shared(); + data_read_req = std::make_shared(); + data_write_req = std::make_shared(); } @@ -331,7 +334,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, SimpleThread* thread = t_info.thread; // use the CPU's statically allocated read request and packet objects - RequestPtr req = &data_read_req; + const RequestPtr &req = data_read_req; if (traceData) traceData->setMem(addr, size, flags); @@ -435,7 +438,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, } // use the CPU's statically allocated write request and packet objects - RequestPtr req = &data_write_req; + const RequestPtr &req = data_write_req; if (traceData) traceData->setMem(addr, size, flags); @@ -545,9 +548,9 @@ AtomicSimpleCPU::tick() if (numThreads > 1) { ContextID cid = threadContexts[curThread]->contextId(); - ifetch_req.setContext(cid); - data_read_req.setContext(cid); - data_write_req.setContext(cid); + ifetch_req->setContext(cid); + data_read_req->setContext(cid); + data_write_req->setContext(cid); } SimpleExecContext& t_info = *threadInfo[curThread]; @@ -577,9 +580,9 @@ AtomicSimpleCPU::tick() bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; if (needToFetch) { - ifetch_req.taskId(taskId()); - setupFetchRequest(&ifetch_req); - fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), + ifetch_req->taskId(taskId()); + setupFetchRequest(ifetch_req); + fault = thread->itb->translateAtomic(ifetch_req, thread->getTC(), BaseTLB::Execute); } @@ -597,7 +600,7 @@ AtomicSimpleCPU::tick() //if (decoder.needMoreBytes()) //{ icache_access = true; - Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); + Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq); ifetch_pkt.dataStatic(&inst); if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index c9dd954bb..addbe234e 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -159,9 +159,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU AtomicCPUDPort dcachePort; bool fastmem; - Request ifetch_req; - Request data_read_req; - Request data_write_req; + RequestPtr ifetch_req; + RequestPtr data_read_req; + RequestPtr data_write_req; bool dcache_access; Tick dcache_latency; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 025c7a3ea..825d3103f 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -468,7 +468,7 @@ BaseSimpleCPU::checkForInterrupts() void -BaseSimpleCPU::setupFetchRequest(RequestPtr req) +BaseSimpleCPU::setupFetchRequest(const RequestPtr &req) { SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 64fa58d92..e62fcf4d1 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -129,7 +129,7 @@ class BaseSimpleCPU : public BaseCPU void checkForInterrupts(); - void setupFetchRequest(RequestPtr req); + void setupFetchRequest(const RequestPtr &req); void preExecute(); void postExecute(); void advancePC(const Fault &fault); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 657c2976f..14e760af9 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -261,7 +261,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt) SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; - RequestPtr req = pkt->req; + const RequestPtr &req = pkt->req; // We're about the issues a locked load, so tell the monitor // to start caring about this address @@ -285,7 +285,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt) } void -TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, +TimingSimpleCPU::sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read) { SimpleExecContext &t_info = *threadInfo[curThread]; @@ -321,8 +321,8 @@ TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, } void -TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2, - RequestPtr req, uint8_t *data, bool read) +TimingSimpleCPU::sendSplitData(const RequestPtr &req1, const RequestPtr &req2, + const RequestPtr &req, uint8_t *data, bool read) { PacketPtr pkt1, pkt2; buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read); @@ -377,14 +377,14 @@ TimingSimpleCPU::translationFault(const Fault &fault) } PacketPtr -TimingSimpleCPU::buildPacket(RequestPtr req, bool read) +TimingSimpleCPU::buildPacket(const RequestPtr &req, bool read) { return read ? Packet::createRead(req) : Packet::createWrite(req); } void TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, - RequestPtr req1, RequestPtr req2, RequestPtr req, + const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) { pkt1 = pkt2 = NULL; @@ -438,8 +438,9 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, if (traceData) traceData->setMem(addr, size, flags); - RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, - thread->contextId()); + RequestPtr req = std::make_shared( + asid, addr, size, flags, dataMasterId(), pc, + thread->contextId()); req->taskId(taskId()); @@ -479,7 +480,7 @@ TimingSimpleCPU::handleWritePacket() SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; - RequestPtr req = dcache_pkt->req; + const RequestPtr &req = dcache_pkt->req; if (req->isMmappedIpr()) { Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); new IprEvent(dcache_pkt, this, clockEdge(delay)); @@ -519,8 +520,9 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, if (traceData) traceData->setMem(addr, size, flags); - RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, - thread->contextId()); + RequestPtr req = std::make_shared( + asid, addr, size, flags, dataMasterId(), pc, + thread->contextId()); req->taskId(taskId()); @@ -620,7 +622,7 @@ TimingSimpleCPU::fetch() if (needToFetch) { _status = BaseSimpleCPU::Running; - RequestPtr ifetch_req = new Request(); + RequestPtr ifetch_req = std::make_shared(); ifetch_req->taskId(taskId()); ifetch_req->setContext(thread->contextId()); setupFetchRequest(ifetch_req); @@ -638,7 +640,7 @@ TimingSimpleCPU::fetch() void -TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, +TimingSimpleCPU::sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc) { if (fault == NoFault) { @@ -659,7 +661,6 @@ TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, } } else { DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr()); - delete req; // fetch fault: advance directly to next instruction (fault handler) _status = BaseSimpleCPU::Running; advanceInst(fault); @@ -775,7 +776,6 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) } if (pkt) { - delete pkt->req; delete pkt; } } @@ -831,7 +831,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) SplitFragmentSenderState * send_state = dynamic_cast(pkt->senderState); assert(send_state); - delete pkt->req; delete pkt; PacketPtr big_pkt = send_state->bigPkt; delete send_state; @@ -866,7 +865,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) traceData = NULL; } - delete pkt->req; delete pkt; postExecute(); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 8498630b4..0300d38eb 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -124,7 +124,7 @@ class TimingSimpleCPU : public BaseSimpleCPU } void - finish(const Fault &fault, RequestPtr req, ThreadContext *tc, + finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) { cpu->sendFetch(fault, req, tc); @@ -133,15 +133,18 @@ class TimingSimpleCPU : public BaseSimpleCPU FetchTranslation fetchTranslation; void threadSnoop(PacketPtr pkt, ThreadID sender); - void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read); - void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req, + void sendData(const RequestPtr &req, + uint8_t *data, uint64_t *res, bool read); + void sendSplitData(const RequestPtr &req1, const RequestPtr &req2, + const RequestPtr &req, uint8_t *data, bool read); void translationFault(const Fault &fault); - PacketPtr buildPacket(RequestPtr req, bool read); + PacketPtr buildPacket(const RequestPtr &req, bool read); void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, - RequestPtr req1, RequestPtr req2, RequestPtr req, + const RequestPtr &req1, const RequestPtr &req2, + const RequestPtr &req, uint8_t *data, bool read); bool handleReadPacket(PacketPtr pkt); @@ -289,7 +292,8 @@ class TimingSimpleCPU : public BaseSimpleCPU Addr addr, Request::Flags flags, uint64_t *res) override; void fetch(); - void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc); + void sendFetch(const Fault &fault, + const RequestPtr &req, ThreadContext *tc); void completeIfetch(PacketPtr ); void completeDataAccess(PacketPtr pkt); void advanceInst(const Fault &fault); -- cgit v1.2.3