From c4cc3145cd1eeed236b5cd3f7b2424bc0761878e Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 16 Oct 2018 16:09:02 +0100 Subject: arch-arm,cpu: Add initial support for Arm SVE This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain - Gabor Dozsa - Giacomo Travaglini Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/cpu/simple_thread.cc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'src/cpu/simple_thread.cc') diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index f86acedd6..c18bac2ef 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2018 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2001-2006 The Regents of The University of Michigan * All rights reserved. * @@ -66,7 +78,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, BaseTLB *_dtb, TheISA::ISA *_isa) : ThreadState(_cpu, _thread_num, _process), isa(_isa), predicate(false), system(_sys), - itb(_itb), dtb(_dtb) + itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) { clearArchRegs(); tc = new ProxyThreadContext(this); @@ -77,7 +89,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, bool use_kernel_stats) : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb), - dtb(_dtb) + dtb(_dtb), decoder(TheISA::Decoder(_isa)) { tc = new ProxyThreadContext(this); -- cgit v1.2.3