From d0e4cdc9c36466a3dbef8c9f9f509cce8f1a6c34 Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 23 Oct 2018 13:51:52 +0100 Subject: cpu: Add a memory access predicate This changeset introduces a new predicate to guard memory accesses. The most immediate use for this is to allow proper handling of predicated-false vector contiguous loads and predicated-false micro-ops of vector gather loads (added in separate changesets). Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991 Tested-by: kokoro Reviewed-by: Bradley Wang Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris --- src/cpu/simple_thread.hh | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/cpu/simple_thread.hh') diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 733047f71..8b5e49a3e 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -117,6 +117,9 @@ class SimpleThread : public ThreadState, public ThreadContext /** Did this instruction execute or is it predicated false */ bool predicate; + /** True if the memory access should be skipped for this instruction */ + bool memAccPredicate; + public: std::string name() const { @@ -576,6 +579,18 @@ class SimpleThread : public ThreadState, public ThreadContext unsigned readStCondFailures() const override { return storeCondFailures; } + bool + readMemAccPredicate() + { + return memAccPredicate; + } + + void + setMemAccPredicate(bool val) + { + memAccPredicate = val; + } + void setStCondFailures(unsigned sc_failures) override { -- cgit v1.2.3