From 326662b01b0fbb7fe4e38cec7a96222d2891808b Mon Sep 17 00:00:00 2001
From: Andreas Sandberg <Andreas.Sandberg@ARM.com>
Date: Wed, 3 Sep 2014 07:42:22 -0400
Subject: arch, cpu: Factor out the ExecContext into a proper base class

We currently generate and compile one version of the ISA code per CPU
model. This is obviously wasting a lot of resources at compile
time. This changeset factors out the interface into a separate
ExecContext class, which also serves as documentation for the
interface between CPUs and the ISA code. While doing so, this
changeset also fixes up interface inconsistencies between the
different CPU models.

The main argument for using one set of ISA code per CPU model has
always been performance as this avoid indirect branches in the
generated code. However, this argument does not hold water. Booting
Linux on a simulated ARM system running in atomic mode
(opt/10.linux-boot/realview-simple-atomic) is actually 2% faster
(compiled using clang 3.4) after applying this patch. Additionally,
compilation time is decreased by 35%.
---
 src/cpu/static_inst.hh | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

(limited to 'src/cpu/static_inst.hh')

diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 375b7d0ba..c4dd3a6b5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -50,19 +50,7 @@
 // forward declarations
 class Packet;
 
-struct O3CPUImpl;
-template <class Impl> class BaseO3DynInst;
-typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
-class InOrderDynInst;
-
-class CheckerCPU;
-class AtomicSimpleCPU;
-class TimingSimpleCPU;
-class InorderCPU;
-namespace Minor
-{
-    class ExecContext;
-};
+class ExecContext;
 
 class SymbolTable;
 
@@ -267,11 +255,25 @@ class StaticInst : public RefCounted, public StaticInstFlags
   public:
     virtual ~StaticInst();
 
-/**
- * The execute() signatures are auto-generated by scons based on the
- * set of CPU models we are compiling in today.
- */
-#include "cpu/static_inst_exec_sigs.hh"
+    virtual Fault execute(ExecContext *xc,
+                          Trace::InstRecord *traceData) const = 0;
+    virtual Fault eaComp(ExecContext *xc,
+                         Trace::InstRecord *traceData) const
+    {
+        panic("eaComp not defined!");
+    }
+
+    virtual Fault initiateAcc(ExecContext *xc,
+                              Trace::InstRecord *traceData) const
+    {
+        panic("initiateAcc not defined!");
+    }
+
+    virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
+                              Trace::InstRecord *traceData) const
+    {
+        panic("completeAcc not defined!");
+    }
 
     virtual void advancePC(TheISA::PCState &pcState) const = 0;
 
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