From 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:12:35 -0400 Subject: Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. --- src/cpu/testers/memtest/memtest.cc | 4 ++-- src/cpu/testers/memtest/memtest.hh | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu/testers/memtest') diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 7ea6ad84b..ea3e5fd9b 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -131,8 +131,8 @@ MemTest::MemTest(const Params *p) dmaOutstanding = false; } -MasterPort & -MemTest::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +MemTest::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "functional") return funcPort; diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 94617c876..cb5f8300f 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -59,8 +59,8 @@ class MemTest : public MemObject // main simulation loop (one cycle) void tick(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Print state of address in memory system via PrintReq (for -- cgit v1.2.3