From d3d24835bcc03ecf312ac6ba7df114656770730f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 7 Mar 2019 03:02:35 -0800 Subject: arch, cpu, dev, gpu, mem, sim, python: start using getPort. Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/cpu/testers/directedtest/RubyDirectedTester.cc | 8 ++++---- src/cpu/testers/directedtest/RubyDirectedTester.hh | 4 ++-- .../garnet_synthetic_traffic/GarnetSyntheticTraffic.cc | 6 +++--- .../garnet_synthetic_traffic/GarnetSyntheticTraffic.hh | 4 ++-- src/cpu/testers/memtest/memtest.cc | 6 +++--- src/cpu/testers/memtest/memtest.hh | 4 ++-- src/cpu/testers/rubytest/RubyTester.cc | 12 ++++++------ src/cpu/testers/rubytest/RubyTester.hh | 4 ++-- src/cpu/testers/traffic_gen/base.cc | 6 +++--- src/cpu/testers/traffic_gen/base.hh | 4 ++-- 10 files changed, 29 insertions(+), 29 deletions(-) (limited to 'src/cpu/testers') diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index be7f3c256..cd367b498 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -78,15 +78,15 @@ RubyDirectedTester::init() generator->setDirectedTester(this); } -BaseMasterPort & -RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyDirectedTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { if (idx >= static_cast(ports.size())) { - panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx); + panic("RubyDirectedTester::getPort: unknown index %d\n", idx); } return *ports[idx]; diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 00278a65e..0f519762c 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -67,8 +67,8 @@ class RubyDirectedTester : public MemObject RubyDirectedTester(const Params *p); ~RubyDirectedTester(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; MasterPort* getCpuPort(int idx); diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc index 0ced9df84..1a07205e6 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc @@ -110,13 +110,13 @@ GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p) name(), id); } -BaseMasterPort & -GarnetSyntheticTraffic::getMasterPort(const std::string &if_name, PortID idx) +Port & +GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx) { if (if_name == "test") return cachePort; else - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh index 3da7e2774..a18f5bbda 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh @@ -64,8 +64,8 @@ class GarnetSyntheticTraffic : public MemObject // main simulation loop (one cycle) void tick(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; /** * Print state of address in memory system via PrintReq (for diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 09e7e88a1..346f88246 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -124,13 +124,13 @@ MemTest::MemTest(const Params *p) schedule(noResponseEvent, clockEdge(progressCheck)); } -BaseMasterPort & -MemTest::getMasterPort(const std::string &if_name, PortID idx) +Port & +MemTest::getPort(const std::string &if_name, PortID idx) { if (if_name == "port") return port; else - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } void diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 023b878c9..8e8f73996 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -77,8 +77,8 @@ class MemTest : public MemObject virtual void regStats(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; protected: diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index 93754467d..cb23688c4 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -128,17 +128,17 @@ RubyTester::init() m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); } -BaseMasterPort & -RubyTester::getMasterPort(const std::string &if_name, PortID idx) +Port & +RubyTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && if_name != "cpuDataPort") { // pass it along to our super class - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } else { if (if_name == "cpuInstPort") { if (idx > m_num_inst_only_ports) { - panic("RubyTester::getMasterPort: unknown inst port %d\n", + panic("RubyTester::getPort: unknown inst port %d\n", idx); } // @@ -147,7 +147,7 @@ RubyTester::getMasterPort(const std::string &if_name, PortID idx) return *readPorts[idx]; } else if (if_name == "cpuInstDataPort") { if (idx > m_num_inst_data_ports) { - panic("RubyTester::getMasterPort: unknown inst+data port %d\n", + panic("RubyTester::getPort: unknown inst+data port %d\n", idx); } int read_idx = idx + m_num_inst_only_ports; @@ -162,7 +162,7 @@ RubyTester::getMasterPort(const std::string &if_name, PortID idx) // if (idx > (static_cast(readPorts.size()) - (m_num_inst_only_ports + m_num_inst_data_ports))) { - panic("RubyTester::getMasterPort: unknown data port %d\n", + panic("RubyTester::getPort: unknown data port %d\n", idx); } int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports; diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 007035977..2509aa2cd 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -94,8 +94,8 @@ class RubyTester : public MemObject RubyTester(const Params *p); ~RubyTester(); - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID); + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; bool isInstOnlyCpuPort(int idx); bool isInstDataCpuPort(int idx); diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc index ad4f67d9d..80fa8a9d6 100644 --- a/src/cpu/testers/traffic_gen/base.cc +++ b/src/cpu/testers/traffic_gen/base.cc @@ -88,13 +88,13 @@ BaseTrafficGen::~BaseTrafficGen() { } -BaseMasterPort& -BaseTrafficGen::getMasterPort(const string& if_name, PortID idx) +Port & +BaseTrafficGen::getPort(const string &if_name, PortID idx) { if (if_name == "port") { return port; } else { - return MemObject::getMasterPort(if_name, idx); + return MemObject::getPort(if_name, idx); } } diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh index 272dcb587..2443e6223 100644 --- a/src/cpu/testers/traffic_gen/base.hh +++ b/src/cpu/testers/traffic_gen/base.hh @@ -182,8 +182,8 @@ class BaseTrafficGen : public MemObject ~BaseTrafficGen(); - BaseMasterPort& getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; + Port &getPort(const std::string &if_name, + PortID idx=InvalidPortID) override; void init() override; -- cgit v1.2.3