From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/cpu/thread_context.cc | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'src/cpu/thread_context.cc')

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index fe1ae69dd..ce7604d3c 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -88,6 +88,15 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
             panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
     }
+
+    // loop through the Vector registers.
+    for (int i = 0; i < TheISA::NumVectorRegs; ++i) {
+        const TheISA::VectorReg &t1 = one->readVectorReg(i);
+        const TheISA::VectorReg &t2 = two->readVectorReg(i);
+        if (t1 != t2)
+            panic("Vector reg idx %d doesn't match", i);
+    }
+
     if (!(one->pcState() == two->pcState()))
         panic("PC state doesn't match.");
     int id1 = one->cpuId();
@@ -127,6 +136,16 @@ serialize(ThreadContext &tc, CheckpointOut &cp)
     SERIALIZE_ARRAY(ccRegs, NumCCRegs);
 #endif
 
+#ifdef ISA_HAS_VECTOR_REGS
+    VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements];
+    for (int i = 0; i < NumVectorRegs; ++i) {
+        const VectorReg &v = tc.readVectorRegFlat(i);
+        for (int j = 0; i < NumVectorRegElements; ++j)
+            vectorRegs[i * NumVectorRegElements + j] = v[j];
+    }
+    SERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements);
+#endif
+
     tc.pcState().serialize(cp);
 
     // thread_num and cpu_id are deterministic from the config
@@ -156,6 +175,17 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
         tc.setCCRegFlat(i, ccRegs[i]);
 #endif
 
+#ifdef ISA_HAS_VECTOR_REGS
+    VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements];
+    UNSERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements);
+    for (int i = 0; i < NumVectorRegs; ++i) {
+        VectorReg v;
+        for (int j = 0; i < NumVectorRegElements; ++j)
+            v[j] = vectorRegs[i * NumVectorRegElements + j];
+        tc.setVectorRegFlat(i, v);
+    }
+#endif
+
     PCState pcState;
     pcState.unserialize(cp);
     tc.pcState(pcState);
-- 
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