From e41197a3f8e93a1c67dddccc96a54e6f560386b2 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Thu, 8 Nov 2007 10:46:41 -0500
Subject: CPU: Add function to explictly compare thread contexts after copying.

--HG--
extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
---
 src/cpu/thread_context.cc | 81 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 src/cpu/thread_context.cc

(limited to 'src/cpu/thread_context.cc')

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
new file mode 100644
index 000000000..10c94027d
--- /dev/null
+++ b/src/cpu/thread_context.cc
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "base/misc.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+
+void
+ThreadContext::compare(ThreadContext *one, ThreadContext *two)
+{
+    DPRINTF(Context, "Comparing thread contexts\n");
+
+    // First loop through the integer registers.
+    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
+        TheISA::IntReg t1 = one->readIntReg(i);
+        TheISA::IntReg t2 = two->readIntReg(i);
+        if (t1 != t2)
+            panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
+                  i, t1, t2);
+    }
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
+        TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
+        TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
+        if (t1 != t2)
+            panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
+                  i, t1, t2);
+    }
+#if FULL_SYSTEM
+    for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
+        TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
+        TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
+        if (t1 != t2)
+            panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
+                  i, t1, t2);
+    }
+#endif
+
+    Addr pc1 = one->readPC();
+    Addr pc2 = two->readPC();
+    if (pc1 != pc2)
+        panic("PCs doesn't match, one: %#x, two: %#x", pc1, pc2);
+
+    Addr npc1 = one->readNextPC();
+    Addr npc2 = two->readNextPC();
+    if (npc1 != npc2)
+        panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2);
+
+    int id1 = one->readCpuId();
+    int id2 = two->readCpuId();
+    if (id1 != id2)
+        panic("CPU ids don't match, one: %d, two: %d", id1, id2);
+}
-- 
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