From 00da08902918da13fccc3f2266b7b2f5d0080708 Mon Sep 17 00:00:00 2001 From: Rekai Gonzalez-Alberquilla Date: Wed, 5 Apr 2017 13:24:00 -0500 Subject: cpu: Added interface for vector reg file This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2705 --- src/cpu/thread_context.hh | 120 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 1 deletion(-) (limited to 'src/cpu/thread_context.hh') diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 43c40481e..66b2f7554 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2012, 2016 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -100,6 +100,8 @@ class ThreadContext typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::CCReg CCReg; typedef TheISA::MiscReg MiscReg; + using VecRegContainer = TheISA::VecRegContainer; + using VecElem = TheISA::VecElem; public: enum Status @@ -212,6 +214,40 @@ class ThreadContext virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; + virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; + virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; + + /** Vector Register Lane Interfaces. */ + /** @{ */ + /** Reads source vector 8bit operand. */ + virtual ConstVecLane8 + readVec8BitLaneReg(const RegId& reg) const = 0; + + /** Reads source vector 16bit operand. */ + virtual ConstVecLane16 + readVec16BitLaneReg(const RegId& reg) const = 0; + + /** Reads source vector 32bit operand. */ + virtual ConstVecLane32 + readVec32BitLaneReg(const RegId& reg) const = 0; + + /** Reads source vector 64bit operand. */ + virtual ConstVecLane64 + readVec64BitLaneReg(const RegId& reg) const = 0; + + /** Write a lane of the destination vector register. */ + virtual void setVecLane(const RegId& reg, + const LaneData& val) = 0; + virtual void setVecLane(const RegId& reg, + const LaneData& val) = 0; + virtual void setVecLane(const RegId& reg, + const LaneData& val) = 0; + virtual void setVecLane(const RegId& reg, + const LaneData& val) = 0; + /** @} */ + + virtual const VecElem& readVecElem(const RegId& reg) const = 0; + virtual CCReg readCCReg(int reg_idx) = 0; virtual void setIntReg(int reg_idx, uint64_t val) = 0; @@ -220,6 +256,10 @@ class ThreadContext virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; + virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; + + virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; + virtual void setCCReg(int reg_idx, CCReg val) = 0; virtual TheISA::PCState pcState() = 0; @@ -303,6 +343,15 @@ class ThreadContext virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; + virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; + virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; + virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0; + + virtual const VecElem& readVecElemFlat(const RegIndex& idx, + const ElemIndex& elemIdx) const = 0; + virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, + const VecElem& val) = 0; + virtual CCReg readCCRegFlat(int idx) = 0; virtual void setCCRegFlat(int idx, CCReg val) = 0; /** @} */ @@ -421,6 +470,52 @@ class ProxyThreadContext : public ThreadContext FloatRegBits readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } + const VecRegContainer& readVecReg(const RegId& reg) const + { return actualTC->readVecReg(reg); } + + VecRegContainer& getWritableVecReg(const RegId& reg) + { return actualTC->getWritableVecReg(reg); } + + /** Vector Register Lane Interfaces. */ + /** @{ */ + /** Reads source vector 8bit operand. */ + ConstVecLane8 + readVec8BitLaneReg(const RegId& reg) const + { return actualTC->readVec8BitLaneReg(reg); } + + /** Reads source vector 16bit operand. */ + ConstVecLane16 + readVec16BitLaneReg(const RegId& reg) const + { return actualTC->readVec16BitLaneReg(reg); } + + /** Reads source vector 32bit operand. */ + ConstVecLane32 + readVec32BitLaneReg(const RegId& reg) const + { return actualTC->readVec32BitLaneReg(reg); } + + /** Reads source vector 64bit operand. */ + ConstVecLane64 + readVec64BitLaneReg(const RegId& reg) const + { return actualTC->readVec64BitLaneReg(reg); } + + /** Write a lane of the destination vector register. */ + virtual void setVecLane(const RegId& reg, + const LaneData& val) + { return actualTC->setVecLane(reg, val); } + virtual void setVecLane(const RegId& reg, + const LaneData& val) + { return actualTC->setVecLane(reg, val); } + virtual void setVecLane(const RegId& reg, + const LaneData& val) + { return actualTC->setVecLane(reg, val); } + virtual void setVecLane(const RegId& reg, + const LaneData& val) + { return actualTC->setVecLane(reg, val); } + /** @} */ + + const VecElem& readVecElem(const RegId& reg) const + { return actualTC->readVecElem(reg); } + CCReg readCCReg(int reg_idx) { return actualTC->readCCReg(reg_idx); } @@ -433,6 +528,12 @@ class ProxyThreadContext : public ThreadContext void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); } + void setVecReg(const RegId& reg, const VecRegContainer& val) + { actualTC->setVecReg(reg, val); } + + void setVecElem(const RegId& reg, const VecElem& val) + { actualTC->setVecElem(reg, val); } + void setCCReg(int reg_idx, CCReg val) { actualTC->setCCReg(reg_idx, val); } @@ -495,6 +596,23 @@ class ProxyThreadContext : public ThreadContext void setFloatRegBitsFlat(int idx, FloatRegBits val) { actualTC->setFloatRegBitsFlat(idx, val); } + const VecRegContainer& readVecRegFlat(int id) const + { return actualTC->readVecRegFlat(id); } + + VecRegContainer& getWritableVecRegFlat(int id) + { return actualTC->getWritableVecRegFlat(id); } + + void setVecRegFlat(int idx, const VecRegContainer& val) + { actualTC->setVecRegFlat(idx, val); } + + const VecElem& readVecElemFlat(const RegIndex& id, + const ElemIndex& elemIndex) const + { return actualTC->readVecElemFlat(id, elemIndex); } + + void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex, + const VecElem& val) + { actualTC->setVecElemFlat(id, elemIndex, val); } + CCReg readCCRegFlat(int idx) { return actualTC->readCCRegFlat(idx); } -- cgit v1.2.3