From 269259004943b80916ec9b6354f2fc00c811c88b Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Tue, 13 Nov 2007 16:58:16 -0500
Subject: Add in files from merge-bare-iron, get them compiling in FS and SE
 mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
---
 src/cpu/thread_context.hh | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/cpu/thread_context.hh')

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 31fdb42c2..fd35efc91 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -238,6 +238,8 @@ class ThreadContext
 
     virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
 
+    virtual void setShadowSet(int css) = 0;
+
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
     virtual unsigned readStCondFailures() = 0;
@@ -407,6 +409,10 @@ class ProxyThreadContext : public ThreadContext
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     { actualTC->setFloatRegBits(reg_idx, val); }
 
+    void setShadowSet(int css){
+      return actualTC->setShadowSet(css);
+    }
+
     uint64_t readPC() { return actualTC->readPC(); }
 
     void setPC(uint64_t val) { actualTC->setPC(val); }
-- 
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