From 753adb38d5471d23315d1bcfc6a744d1c6e03975 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Fri, 22 Jun 2007 19:03:42 -0400
Subject: mips import pt. 1

src/arch/mips/SConscript:
    "mips import pt.1".

--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
---
 src/cpu/thread_context.hh | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/cpu/thread_context.hh')

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 05c409c95..3706d8543 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -234,6 +234,10 @@ class ThreadContext
 
     virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
+    virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
+
+    virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
+
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
     virtual unsigned readStCondFailures() = 0;
-- 
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