From af6aaf258171027af8d3cf0ef86dddff501a3ccb Mon Sep 17 00:00:00 2001
From: Geoffrey Blake <geoffrey.blake@arm.com>
Date: Tue, 31 Jan 2012 07:46:03 -0800
Subject: CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU.  These changes have only been tested with the ARM ISA.  Other
ISAs potentially require modification.
---
 src/cpu/thread_context.hh | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'src/cpu/thread_context.hh')

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index d80d26e3d..946c35249 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -39,6 +51,7 @@
 #include "base/types.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
+#include "config/use_checker.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
 // DTB pointers.
@@ -121,6 +134,10 @@ class ThreadContext
 
     virtual TheISA::TLB *getDTBPtr() = 0;
 
+#if USE_CHECKER
+    virtual BaseCPU *getCheckerCpuPtr() = 0;
+#endif
+
     virtual Decoder *getDecoderPtr() = 0;
 
     virtual System *getSystemPtr() = 0;
@@ -205,6 +222,10 @@ class ThreadContext
 
     virtual void pcState(const TheISA::PCState &val) = 0;
 
+#if USE_CHECKER
+    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
+#endif
+
     virtual Addr instAddr() = 0;
 
     virtual Addr nextInstAddr() = 0;
@@ -296,6 +317,10 @@ class ProxyThreadContext : public ThreadContext
 
     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
+#if USE_CHECKER
+    BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
+#endif
+
     Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
@@ -382,6 +407,10 @@ class ProxyThreadContext : public ThreadContext
 
     void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
 
+#if USE_CHECKER
+    void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
+#endif
+
     Addr instAddr() { return actualTC->instAddr(); }
     Addr nextInstAddr() { return actualTC->nextInstAddr(); }
     MicroPC microPC() { return actualTC->microPC(); }
-- 
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