From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001 From: Nathanael Premillieu Date: Wed, 5 Apr 2017 12:46:06 -0500 Subject: arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2700 --- src/cpu/timing_expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/timing_expr.cc') diff --git a/src/cpu/timing_expr.cc b/src/cpu/timing_expr.cc index 88bc5476f..99b4eb6aa 100644 --- a/src/cpu/timing_expr.cc +++ b/src/cpu/timing_expr.cc @@ -58,7 +58,7 @@ TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_, uint64_t TimingExprSrcReg::eval(TimingExprEvalContext &context) { - return context.inst->srcRegIdx(index); + return context.inst->srcRegIdx(index).regIdx; } uint64_t TimingExprReadIntReg::eval(TimingExprEvalContext &context) -- cgit v1.2.3