From 7584c390ebbb890642468a7cfd40aaa52699684e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 17 Aug 2019 01:40:39 -0700 Subject: cpu: Make get(Data|Inst)Port return a Port and not a MasterPort. No caller uses any of the MasterPort specific properties of these function's return values, so we can instead return a reference to the base Port class. This makes it possible for the data and inst ports to be of any port type, not just gem5 style MasterPorts. This makes life simpler for, for example, systemc based CPUs which might have TLM ports. It also makes it possible for any two CPUs which have compatible ports to be switched between, as long as the ports they use support being unbound. Unfortunately that does not include TLM or systemc ports which are bound permanently. Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240 Tested-by: kokoro Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Maintainer: Gabe Black --- src/cpu/trace/trace_cpu.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/trace') diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh index c873a349f..ebc14ca81 100644 --- a/src/cpu/trace/trace_cpu.hh +++ b/src/cpu/trace/trace_cpu.hh @@ -1146,10 +1146,10 @@ class TraceCPU : public BaseCPU public: /** Used to get a reference to the icache port. */ - MasterPort &getInstPort() { return icachePort; } + Port &getInstPort() { return icachePort; } /** Used to get a reference to the dcache port. */ - MasterPort &getDataPort() { return dcachePort; } + Port &getDataPort() { return dcachePort; } void regStats(); }; -- cgit v1.2.3