From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 4 Jun 2018 09:40:19 +0100
Subject: misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
src/cpu/trace/trace_cpu.cc | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
(limited to 'src/cpu/trace')
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 77755e888..2b198e966 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -662,9 +662,11 @@ TraceCPU::ElasticDataGen::executeMemReq(GraphNode* node_ptr)
}
// Create a request and the packet containing request
- Request* req = new Request(node_ptr->physAddr, node_ptr->size,
- node_ptr->flags, masterID, node_ptr->seqNum,
- ContextID(0));
+ auto req = std::make_shared<Request>(
+ node_ptr->physAddr, node_ptr->size,
+ node_ptr->flags, masterID, node_ptr->seqNum,
+ ContextID(0));
+
req->setPC(node_ptr->pc);
// If virtual address is valid, set the asid and virtual address fields
// of the request.
@@ -1158,7 +1160,7 @@ TraceCPU::FixedRetryGen::send(Addr addr, unsigned size, const MemCmd& cmd,
{
// Create new request
- Request* req = new Request(addr, size, flags, masterID);
+ auto req = std::make_shared<Request>(addr, size, flags, masterID);
req->setPC(pc);
// If this is not done it triggers assert in L1 cache for invalid contextId
@@ -1224,8 +1226,7 @@ bool
TraceCPU::IcachePort::recvTimingResp(PacketPtr pkt)
{
// All responses on the instruction fetch side are ignored. Simply delete
- // the request and packet to free allocated memory
- delete pkt->req;
+ // the packet to free allocated memory
delete pkt;
return true;
@@ -1250,9 +1251,8 @@ TraceCPU::DcachePort::recvTimingResp(PacketPtr pkt)
// Handle the responses for data memory requests which is done inside the
// elastic data generator
owner->dcacheRecvTimingResp(pkt);
- // After processing the response delete the request and packet to free
+ // After processing the response delete the packet to free
// memory
- delete pkt->req;
delete pkt;
return true;
--
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