From 005892719047c3b4b383d9aeeeb481039518f661 Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Mon, 15 Nov 2010 14:04:04 -0600 Subject: CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. --- src/cpu/FuncUnit.py | 17 +++++++++++++++++ src/cpu/o3/FUPool.py | 2 +- src/cpu/o3/FuncUnitConfig.py | 35 +++++++++++++++++++++++++++++++++++ src/cpu/op_class.hh | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index ad2d1b87b..002546f26 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -1,3 +1,15 @@ +# Copyright (c) 2010 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -32,6 +44,11 @@ from m5.params import * class OpClass(Enum): vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', + 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', + 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', + 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', + 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', + 'SimdFloatMultAcc', 'SimdFloatSqrt', 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] class OpDesc(SimObject): diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py index 4f07f9867..1d3afbc6b 100644 --- a/src/cpu/o3/FUPool.py +++ b/src/cpu/o3/FUPool.py @@ -37,4 +37,4 @@ class FUPool(SimObject): class DefaultFUPool(FUPool): FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), - WritePort(), RdWrPort(), IprPort() ] + SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ] diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py index 954381f86..34c56163d 100644 --- a/src/cpu/o3/FuncUnitConfig.py +++ b/src/cpu/o3/FuncUnitConfig.py @@ -1,3 +1,15 @@ +# Copyright (c) 2010 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -51,6 +63,29 @@ class FP_MultDiv(FUDesc): OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] count = 2 +class SIMD_Unit(FUDesc): + opList = [ OpDesc(opClass='SimdAdd'), + OpDesc(opClass='SimdAddAcc'), + OpDesc(opClass='SimdAlu'), + OpDesc(opClass='SimdCmp'), + OpDesc(opClass='SimdCvt'), + OpDesc(opClass='SimdMisc'), + OpDesc(opClass='SimdMult'), + OpDesc(opClass='SimdMultAcc'), + OpDesc(opClass='SimdShift'), + OpDesc(opClass='SimdShiftAcc'), + OpDesc(opClass='SimdSqrt'), + OpDesc(opClass='SimdFloatAdd'), + OpDesc(opClass='SimdFloatAlu'), + OpDesc(opClass='SimdFloatCmp'), + OpDesc(opClass='SimdFloatCvt'), + OpDesc(opClass='SimdFloatDiv'), + OpDesc(opClass='SimdFloatMisc'), + OpDesc(opClass='SimdFloatMult'), + OpDesc(opClass='SimdFloatMultAcc'), + OpDesc(opClass='SimdFloatSqrt') ] + count = 4 + class ReadPort(FUDesc): opList = [ OpDesc(opClass='MemRead') ] count = 0 diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh index 8cbe10f91..2dc7a3674 100644 --- a/src/cpu/op_class.hh +++ b/src/cpu/op_class.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2003-2005 The Regents of The University of Michigan * All rights reserved. * @@ -50,6 +62,26 @@ const OpClass FloatCvtOp = Enums::FloatCvt; const OpClass FloatMultOp = Enums::FloatMult; const OpClass FloatDivOp = Enums::FloatDiv; const OpClass FloatSqrtOp = Enums::FloatSqrt; +const OpClass SimdAddOp = Enums::SimdAdd; +const OpClass SimdAddAccOp = Enums::SimdAddAcc; +const OpClass SimdAluOp = Enums::SimdAlu; +const OpClass SimdCmpOp = Enums::SimdCmp; +const OpClass SimdCvtOp = Enums::SimdCvt; +const OpClass SimdMiscOp = Enums::SimdMisc; +const OpClass SimdMultOp = Enums::SimdMult; +const OpClass SimdMultAccOp = Enums::SimdMultAcc; +const OpClass SimdShiftOp = Enums::SimdShift; +const OpClass SimdShiftAccOp = Enums::SimdShiftAcc; +const OpClass SimdSqrtOp = Enums::SimdSqrt; +const OpClass SimdFloatAddOp = Enums::SimdFloatAdd; +const OpClass SimdFloatAluOp = Enums::SimdFloatAlu; +const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp; +const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt; +const OpClass SimdFloatDivOp = Enums::SimdFloatDiv; +const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; +const OpClass SimdFloatMultOp = Enums::SimdFloatMult; +const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; +const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; const OpClass MemReadOp = Enums::MemRead; const OpClass MemWriteOp = Enums::MemWrite; const OpClass IprAccessOp = Enums::IprAccess; -- cgit v1.2.3